ADVANCED COMPUTER ARCHITECTURE Notes - Multiprocessors and Thread-Level Parallelism, 1, Study notes for Advanced Computer Architecture. Punjab Technical University (PTU)

Advanced Computer Architecture

Description: Notes on: Multiprocessors, Symmetric Shared Memory Architectures, Cache Coherence in Multiprocessors, Basic Schemes for Enforcing Coherence, Snooping, Snooping Protocols, broadcast protocol, Distributed Shared-Memory Architectures, Basic Hardware Primitives, Barrier Synchronization, Larger-Scale Multiprocessors, Simultaneous Multithreading, Superscalar,SMT processors
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Multiprocessors and Thread-Level Parallelism
1. Explain Symmetric Shared-Memory Architecture and How to reduce Cache
coherence problem in Symmetric Shared Memory architectures:
Symmetric Shared Memory Architectures:
The Symmetric Shared Memory Architecture consists of several processors with a single
physical memory shared by all processors through a shared bus which is shown below.
` Small-scale shared-memory machines usually support the caching of both shared
and private data. Private data is used by a single processor, while shared data is used by
multiple processors, essentially providing communication among the processors through
reads and writes of the shared data. When a private item is cached, its location is
migrated to the cache, reducing the average access time as well as the memory bandwidth
required. Since no other processor uses the data, the program behavior is identical to that
in a uniprocessor.
Cache Coherence in Multiprocessors:
Introduction of caches caused a coherence problem for I/O operations, The same problem
exists in the case of multiprocessors, because the view of memory held by two different
processors is through their individual caches. Figure 6.7 illustrates the problem and
shows how two different processors can have two different values for the same location.
This difficulty s generally referred to as the cache-coherence problem.
Time Event
contents for
contents for
contents for
location X
1 CPU A reads X 1 1
CPU B reads
3 CPU A stores 0 into X 0 1 0
FIGURE 6.7 The cache-coherence problem for a single memory location (X), read
and written by two processors (A and B). We initially assume that neither cache
contains the variable and that X has the value 1. We also assume a write-through cache; a
write-back cache adds some additional but similar complications. After the value of X
has been written by A, A’s cache and the memory both contain the new value, but B’s
cache does not, and if B reads the value of X, it will receive 1!
Informally, we could say that a memory system is coherent if any read of a data item
returns the most recently written value of that data item. This simple definition contains
two different aspects of memory system behavior, both of which are critical to writing
correct shared-memory programs. The first aspect, called coherence, defines what values
can be returned by a read. The second aspect, called consistency, determines when a
written value will be returned by a read. Let’s look at coherence first.
A memory system is coherent if
1 A read by a processor, P, to a location X that follows a write by P to X, with no
writes of X by another processor occurring between the write and the read by P, always
returns the value written by P.
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renuka.devi.94211 - Jawaharlal Nehru Technological University

good one

06/05/13 10:47
hishamnajam - Pakistan Institute of Engineering and Applied Sciences, Islamabad (PIEAS)


07/01/13 20:30
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