Addressing Mode - Intro to Computer Architecture - Homework, Exercises for Computer Architecture. Shree Ram Swarup College of Engineering & Management

Computer Architecture

Description: In the course of intro to computer architecture, the main points are:Addressing Mode, 16-Bit Number, 24-Bit Instruction, Auto-Increment Register-Indirect Addressing Mode, Speed Efficiency, Appropriate Register, Multiplication Technique, Division Technique, Non-Restoring Division
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1. [add ext blankblankblank ]
Semantics: r1r0r1r0r3r2where r1r0means the 16-bit number formed by concatenating r1s data
to r0s data with the latter being the LS-byte and the
former
the MS-byte. (r2r3is similarly defined).
add ext opcode = 001111
2. (a) Design the format of a 24-bit instruction to perform a load word lw+ using the auto-increment
register-indirect addressing mode with the semantics riMem rj;rjrjX. Note the initial (non-
incremented) value of rjis to be used for the address of the data word to be obtained from memory.
Clearly explain the format and what it means. Next, design the CU states for executing the lw+
instruction.
lw+ opcode = 010000
Hint: Just like in the sw instruction from Project 1, the 1st or least significant 2 bytes will have the
opcode and other information that the CU needs immediately to start processing the first part of the
instruction (riMem rj). The last (most significant) 8 bits of the instruction can be fetched after
the initial part is done and loaded into an appropriate register (mdr, ir0, ir1, etc.) so that it enables the
2nd part of the instruction (rjrjX) to be completed.
(b) Comment on the speed efficiency of using the 24-bit lw+ instruction above versus using two 16-bit
instructions load ind and add imm (you did these in Project 1) to accomplish the same effect as the lw+
instruction.
3. [mul slow rirjrk] – type 1
Semantics: rirjrkusing the slow multiplication technique given below (repeated addition with
no shifting). Note that either of rj,rkcould be negative.
mul slow opcode = 010001
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4. [div slow rirjrk] – type 1
Semantics: rirjrkusing the slow division technique given below (repeated subtraction with no
shifting). Note that either of rj,rkcould be negative.
div slow opcode = 010010
5. [div fast rirjrk] – type 1
Semantics: rirjrkusing the fast non-restoring division technique (see lecture notes on “Iterative
Division”).
div fast opcode = 010011
For division, also assume that the Dand Vspecified in rj,rkare unsigned integers represented in 7
bits (MSB–bit 7– is 0, while the numbers are represented in bits 6 to 0). This is needed in order to get
the negative V(for subtraction) in 2’s complement that is representable in 8 bits (this is automatically
done by choosing alu sel SUB so you don’t have to worry about it).
For the (slow) multiplication instruction use the following method for performing c a b:
1. c0; sign 0
2. If b0 then b b /* convert bto a +ve # */
sign = not(sign)
3. if (b == 0) then goto step 5 /* final result is in c*/
else c c a
4. b b 1; goto step 3.
5. if (sign=1) then c c /* restore correct sign to the result */
For the slow division instruction use the following method for performing c a b (we assume b0):
1. c0; sign 0
2. If b0 then b b /* convert bto a +ve # */
sign = not(sign)
3. If a0 then a b /* convert ato a +ve # */
sign = not(sign)
4. a a b
If (a0) then goto step 6 /* quotient is in c*/
else c c 1; goto step 4
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