Computer Achitecture and org - Register and Register Files - Saritha, undefined for Computer Architecture and Organization. Vellore Institute of Technology (VIT) University

Computer Architecture and Organization

Description: Detail Summery about Register and Register Files, Memory Hierarchy, User-Visible Registers, General Purpose, Condition Codes, Example Register Organizations.
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Register and Register Files

Register and Register Files

Registers • Memory Hierarchy

– Registers – Cache memory – Main memory – Secondary memory

• At higher levels of hierarchy, memory is faster, smaller and more expensive.

• Number and function vary between processor designs - one of the major design decisions

• Top level of memory hierarchy • Two roles

– User-visible registers – Control and status registers

User-Visible Registers

• General Purpose • Data • Address • Condition Codes

General Purpose Registers • True general purpose registers – register can contain the

operand for any Opcode • Restricted – used for specific operations – floating point

and stack operations. (dedicated registers) • Data registers – used only to hold data and cannot be

employed in the calculation of an operand address – Accumulator (AC)

• Address registers – Segment registers – holds the address of the base of the

segment. – Index registers – used for indexed addressing and may be auto-

indexed – Stack pointer – points to the top of the stack (if there is a user-

visible stack addressing, stack is in memory)

Design Issues

• Specialized registers – Implicit in the Opcode, Saves bits (small instructions)

– because of less number of specialized registers, Less flexibility

• General purpose registers – Increased instruction size, increased flexibility and

programmer options • Number of GP, data + address registers: 8 to 32

is optimum – Fewer registers result in more memory references

How big?

• Large enough to hold full address • Large enough to hold data of most data

types • But often possible to combine two data

registers or two address registers by using more complex addressing (e.g. page and offset)

Condition Code Registers – Flags

• Condition codes are bits set by the CPU hardware as the result of operations.

• Machine instructions allow these bits to be read by implicit reference.

• Programmer cannot alter them • In some machines, sub-routine call will result in the

automatic saving of all user-visible registers, to be restored on return.

• Sets of individual bits, flags – e.g. result of last operation was zero

• Can be read by programs – e.g. Jump if zero – simplifies branch taking

Control & Status Registers • Not visible to the user • May be visible in a control or operating system

mode (supervisory mode) • Registers essential to instruction execution:

– Program Counter (PC) – Instruction Register (IR) – Memory Address Register (MAR) – connects to

address bus – Memory Buffer Register (MBR) – connects to data

bus, feeds other registers

Program Status Word

• Contains status information • Condition Codes:

– Sign (of last result) – Zero (last result) – Carry (multiword arithmetic) – Equal (two latest results) – Overflow – Interrupts enabled/disabled – Supervisor/user mode

Example Register Organizations

Register Files (RF)

• Set of general purpose registers. • It functions as small RAM and implemented

using fast RAM technology. • RF needs several access ports for

simultaneously reading from or writing to several different registers. Hence RF is realized as multiport RAM.

• A standard RAM has just one access port with an associated address bus and data bus.

A register file with three access ports - symbol

Port C

Port A Port BAddress A Address B

Address C

Register File RF

22

2

16 16

16

Data out A Data out B

Data in C

A Register File with three access ports – logic diagram

4-way 16-bit demultiplexer

4-way 16-bit multiplexer

4-way 16-bit multiplexer

16-bit register R3 16-bit register R2 16-bit register R1 16-bit register R0

● ●

Data out A Data out B

Write address C

Read address A

Read address B16 16

16

16 16

16

16 16 16 16

16

Data in C

S

S S 2

2

2

Ex: R3 ← R1 + R2 Read Address A = 01 Read Address B = 10 Write Address C = 11

01

11

0101

A Register File with three access ports – logic diagram

4-way 16-bit demultiplexer

4-way 16-bit multiplexer

4-way 16-bit multiplexer

16-bit register R3 16-bit register R2 16-bit register R1 16-bit register R0

● ●

Data out A Data out B

Write address C

Read address A

Read address B16 16

16

16 16

16

16 16 16 16

16

Data in C

S

S S 2

2

2

Ex: R3 ← R1 + R2 Read Address A = 01 Read Address B = 10 Write Address C = 11

01 10

11

01010110

1011

Quiz • If the 8 registers are used

– How many bits are needed for read/write address? – What is the size of the demultiplexer and multiplexer

required? – How many multiplexers and demultiplexer’s are

required? • If 4 multiplexers are used, how many parallel

reads can be performed? • If 2 demultiplexers are used, how many parallel

writes can be performed? • Give an example with 4 parallel reads and 2

parallel writes.(how many registers are required?)

References

• W. Stallings, Computer organization and architecture, Prentice-Hall,2000

• J. P. Hayes, Computer system architecture, McGraw Hill

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