Concurrent Signal - Sequential Logic Design - Lecture Slides, Slides for Digital Logic Design. Birla Institute of Technology and Science

Digital Logic Design

Description: Its one of the Sequential Logic Design lectures. Its key points are: Concurrent Signal, Decoders Using Structural, Concurrent Logic Behavior, Expression Changes, Left Hand Side, Architecture, Gates Operate, Gate Relative, Actual Value, Cause a Glitch
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Lecture #10
1. VHDL : Concurrent Signal Assignments
2. Decoders using Structural VHDL
1. HW #4 due
2. HW #5 assigned
Sequential Logic Design
Concurrent Signal Assignments
- the way that our designs are simulated is important in modeling real HW behavior
- components are executed concurrently (i.e., at the same time)
- VHDL gives us another method to describe concurrent logic behavior called
"Concurrent Signal Assignments"
- we simply list our signal assignments (<=) after the "begin" statement in the architecture
- each time any signal on the Right Hand Side (RHS) of the expression changes,
the Left Hand Side (LHS) of the assignment is updated.
- operators can be included (and, or, +, …)
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