Concurrent Signal - Sequential Logic Design - Lecture Slides, Slides for Digital Logic Design. Birla Institute of Technology and Science

Digital Logic Design

Description: Its one of the Sequential Logic Design lectures. Its key points are: Concurrent Signal, Decoders Using Structural, Concurrent Logic Behavior, Expression Changes, Left Hand Side, Architecture, Gates Operate, Gate Relative, Actual Value, Cause a Glitch
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Lecture #10
1. VHDL : Concurrent Signal Assignments
2. Decoders using Structural VHDL
1. HW #4 due
2. HW #5 assigned
Sequential Logic Design
Concurrent Signal Assignments
- the way that our designs are simulated is important in modeling real HW behavior
- components are executed concurrently (i.e., at the same time)
- VHDL gives us another method to describe concurrent logic behavior called
"Concurrent Signal Assignments"
- we simply list our signal assignments (<=) after the "begin" statement in the architecture
- each time any signal on the Right Hand Side (RHS) of the expression changes,
the Left Hand Side (LHS) of the assignment is updated.
- operators can be included (and, or, +, …)
Concurrent Signal Assignments
Concurrent Signal Assignment Example
entity TOP is
port (A,B,C : in STD_LOGIC;
X : out STD_LOGIC);
end entity TOP;
architecture TOP_arch of TOP is
signal node1 : STD_LOGIC;
node1 <= A xor B;
X <= node1 or C;
end architecture TOP_arch;
Concurrent Signal Assignments
Concurrent Signal Assignment Example
node1 <= A xor B;
X <= node1 or C;
- if these are executed concurrently, does it model the real behavior of this circuit?
Yes, that is how these gates operate. We can see that there may be timing that
needs to be considered….
- When does C get to the OR gate relative to (A B)?
- Could this cause a glitch on X? What about a delay in the actual value?
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