# Digital Computers - Organization and Logical Design - Exam, Exams for Organization Theory and Design. Bengal Engineering & Science University

## Organization Theory and Design

Description: Main points of this exam paper are: Organization, Logical Design, Digital Computers, Simulation, Blanks Below, Instruction, Corresponding Labeled, Simulation Output, Negate, Immediate Load
Showing pages  1  -  4  of  9
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1. (10 points). The figure below shows a simulation of the washu-1 processor, with some items
blanked out. Fill in the blanks below with the correct value from the corresponding labeled
blank in the simulation output. The instruction set appears at the bottom of the page.
A. ______________ B. ______________ C. ______________
D. ______________ E. ______________
0000 halt
0001 negate
4xxx direct store
5xxx indirect store
6xxx branch
7xxx branch if zero
8xxx branch if positive
9xxx branch if negative
dxxx and
CSE 260 – Digital Computers: Organization and Logical Design
Midterm
Jon Turner 2/28/2008
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2. (8 points) Draw a transistor-level diagram (using n-FETs and p-FETs) of a NAND gate with
3 inputs, A, B and C.
Suppose all three inputs are high initially and then A goes low, causing the output of the
NAND gate to go from low to high. Let tLH be the time for this high to low transition. Now,
suppose that input A goes high again, causing the output to go from high to low. Let tHL be
the time for this low to high transition. Which is larger, tLH or tHL? Explain why.
How much larger? Assume that the on-resistance of an n-FET is the same as the on-
resistance of a p-FET.
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3. (6 points) The circuit shown below is a 4 bit adder, implemented using LUT4s. The outputs
(S3..S0) = (A3..A0) + (B3..B0). What are the logic equations implemented by the LUTs for
signals S2 and C3 (these LUTs are highlighted with a bold outline)? What is the worst-case
propagation delay of this circuit, if each LUT has a delay of 1 ns.
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4. (15 points) The diagram at right shows a combinational circuit with four bit inputs A and B
plus a four bit output X. It also has a one bit input, Zin and a one bit output Zout. How many
LUT4s are needed to implement this circuit?
Complete the VHDL module shown below so that it implements the circuit shown.
entity foo is port (
);
end foo;
architecture a1 of foo is
begin
process( ) begin
end process;
end a1;