Hardware Solutions For The Critical Section Problem-Operating Systems-Lecture Notes, Study notes for Operating System. Cochin University of Science and Technology

Operating System

Description: Operating Systems is necessary course in Computer Science. Its about threading, process scheduling, deadlocks, memory management etc. This lecture includes: Hardware, Solution, Semaphores, Critical, Section, Process, Structure, Algorithm, Data, Common
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Operating Systems [CS-604] Lecture No. 21
Operating Systems
Lecture No. 21
Reading Material
Chapter 7 of the textbook
Lecture 21 on Virtual TV
Hardware solutions
Hardware Solutions for the Critical Section Problem
In this section, we discuss some simple hardware (CPU) instructions that can be used to
provide synchronization between processes and are available on many systems.
The critical section problem can be solved simply in a uniprocessor environment if
we could forbid interrupts to occur while a shared variable is being modified. In this
manner, we could be sure that the current sequence of instructions would be run, so no
unexpected modifications could be made to the shared variable.
Unfortunately this solution is not feasible in a multiprocessing environment, as
disabling interrupts can be time consuming as the message is passed to all processors.
This message passing delays entry into each critical section, and system efficiency
Normally, access to a memory location excludes other accesses to that same location.
Designers have proposed machine instructions that perform two operations atomically
(indivisibly) on the same memory location (e.g., reading and writing). The execution of
such an instruction is also mutually exclusive (even on Multiprocessors). They can be
used to provide mutual exclusion but other mechanisms are needed to satisfy the other
two requirements of a good solution to the critical section problem.
We can use these special instructions to solve the critical section problem. These
instructions are TestAndSet (also known as TestAndSetLock; TSL) and Swap. The
semantics of the TestAndSet instruction are as follows:
boolean TestAndSet(Boolean &target)
boolean rv=target;
return rv;
The semantics simply say that the instruction saves the current value of ‘target’, set it to
true, and returns the saved value.
The important characteristic is that this instruction is executed atomically. Thus if two
TestAndSet instructions are executed simultaneously, they will be executed sequentially
in some arbitrary order.
If the machine supports TestAndSet instruction, then we can implement mutual
exclusion by declaring a Boolean variable lock, initialized to false. The structure of
process Pi becomes:
while (TestAndSet(lock)) ;
Critical section
Remainder section
} while(1);
The above TSL-based solution is no good because even though mutual exclusion and
progress are satisfied, bounded waiting is not.
The semantics of the Swap instruction, another atomic instruction, are, as expected, as
boolean Swap(boolean &a, boolean &b)
boolean temp=a;
If the machine supports the Swap instruction, mutual exclusion can be implemented
as follows. A global Boolean variable lock is declared and is initialized to false. In
addition each process also has a local Boolean variable key. The structure of process Pi
while(key == true)
Critical section
Remainder section
} while(1);
Just like the TSL-based solution shown in this section, the above Swap-based solution is
not good because even though mutual exclusion and progress are satisfied, bounded
waiting is not. In the next lecture, we will discuss a good solution for the critical section
problem by using the hardware instructions.
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