Vertical Redundancy Check-Computer Networks-Assignment, Exercises for Computer Networks. Birla Institute of Technology and Science

Computer Networks

Description: This is an introductory course in Data Communication and Computer Networks. The course is designed with objectives: Provide solid foundation in the field of data communication and computer networks, give practical experience on networks and networking devices, introduce the cutting edge technologies. This assignment main points are: Drawback, Vertical, Redundancy, Check, Data, Transmission, Errors, Longitudinal, Horizontal, Arranging
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Assignment 2
Question 1: What is the drawback of VRC
Vertical Redundancy Check is a way of error checking by attaching a parity bit to each byte
of data to be transmitted, which is then tested to determine if the transmission is correct.
The resulting parity bit is constructed by XORing the word. The result is a "1" if there is an odd
number of 1s, and a "0" if there is an even number of 1s in the word.
Draw Back:
This method is unreliable, because if there are even number of errors in the data, the error
will go undetected.
Question 2: Calculate the LRC of the following data: [HEX] 864C9BF3
In telecommunication, a longitudinal redundancy check (LRC) or horizontal redundancy
check is a form of redundancy check that is applied independently to each of a parallel group
of bit streams. The data must be divided into transmission blocks, to which the additional
check data is added.
Data: 1000 0110 0100 1100 1001 1011 1111 0011
Arranging data:
1 0 0 0
0 1 1 0
0 1 0 0
1 1 0 0
1 0 0 1
1 0 1 1
1 1 1 1
0 0 1 1
1 0 0 0 (Parity bit calculated for every column)
Transmitted Data: 1000 0110 0100 1100 1001 1011 1111 0011 1000
VRC:
Solution:
LRC:
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P a g e | 2
Assignment 2
Question 3: A: For P=110101 and M=1011010001, Find CRC?
B: In CRC error Detection scheme, choose P(x)=x4+x+1. Encode the bits
10111011011?
1 1 0 1 1 0 1
110101 / 1 0 1 1 0 1 0 0 0 1 0 0 0 0 0
1 1 0 1 0 1 : : : : : : : : :
0 1 1 0 0 0 0 : : : : : : : :
1 1 0 1 0 1 : : : : : : : :
0 0 0 1 0 1 0 0 1 : : : : :
1 1 0 1 0 1 : : : : :
0 1 1 1 0 0 0 : : : :
1 1 0 1 0 1 : : : :
0 0 1 1 0 1 0 0 : :
1 1 0 1 0 1 : :
0 0 0 0 0 1 0 0 <= FCS
The FCS is: X2
Transmitted bits: 1 0 1 1 0 1 0 0 0 1 0 0 1 0 0
1 1 0 1 0 1 1
10011 / 1 0 1 1 1 0 1 1 0 1 1 0 0 0 0
1 0 0 1 1 : : : : : : : : : :
0 0 1 0 0 0 1 : : : : : : : :
1 0 0 1 1 : : : : : : : :
0 0 0 1 0 1 0 1 : : : : :
1 0 0 1 1 : : : : :
0 0 1 1 0 1 0 : : :
1 0 0 1 1 : : :
0 1 0 0 1 0 : :
1 0 0 1 1 : :
0 0 0 0 1 0 0 <= FCS
Predetermined Divisor: 10011
FCS = X3
Transmitted bits: 1 0 1 1 1 0 1 1 0 1 1 0 1 0 0
Part A:
Part B:
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