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1. (10 points). The figure below shows a simulation of the washu-1 processor, with some items blanked out. Fill in the blanks below with the correct value from the corresponding labeled blank in the simulation output. The instruction set appears at the bottom of the page.
A. ______________ B. ______________ C. ______________
D. ______________ E. ______________
0000 halt 0001 negate 1xxx immediate load 2xxx direct load 3xxx indirect load 4xxx direct store 5xxx indirect store
6xxx branch 7xxx branch if zero 8xxx branch if positive 9xxx branch if negative axxx add dxxx and
CSE 260 – Digital Computers: Organization and Logical Design Midterm
Jon Turner 2/28/2008
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2. (8 points) Draw a transistor-level diagram (using n-FETs and p-FETs) of a NAND gate with 3 inputs, A, B and C.
Suppose all three inputs are high initially and then A goes low, causing the output of the NAND gate to go from low to high. Let tLH be the time for this high to low transition. Now, suppose that input A goes high again, causing the output to go from high to low. Let tHL be the time for this low to high transition. Which is larger, tLH or tHL? Explain why.
How much larger? Assume that the on-resistance of an n-FET is the same as the on- resistance of a p-FET.
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3. (6 points) The circuit shown below is a 4 bit adder, implemented using LUT4s. The outputs (S3..S0) = (A3..A0) + (B3..B0). What are the logic equations implemented by the LUTs for signals S2 and C3 (these LUTs are highlighted with a bold outline)? What is the worst-case propagation delay of this circuit, if each LUT has a delay of 1 ns.
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4. (15 points) The diagram at right shows a combinational circuit with four bit inputs A and B plus a four bit output X. It also has a one bit input, Zin and a one bit output Zout. How many LUT4s are needed to implement this circuit?
Complete the VHDL module shown below so that it implements the circuit shown.
entity foo is port (
); end foo; architecture a1 of foo is begin process( ) begin
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5. (20 points) Complete the diagram shown below to show the circuit implemented by the following VHDL specification.
entity foo is port( clk: in std_logic; A, B: in std_logic_vector(7 downto 0); X, Y: out std_logic_vector(7 downto 0); end entity; architecture bar of foo is type stateType is (tennis, pingpong, archery) signal state: stateType; signal Z: std_logic_vector(7 downto 0); begin process (clk,A,Z) begin if rising_edge(clk) then Z <= B; case state is when tennis => if A > B then X <= B; state <= archery; end if; when pingpong => if B > Z then Z <= A xor B; state <= tennis; end if; when others => X <= A; state <= pingpong; end case; end if Y <= A + Z; end process; end bar;
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6. (20 points). A pulse pair detector is a circuit with a single input D and an output X, which detects closely spaced pairs of pulses. A pulse is a 0, followed by one or more 1s, followed by a 0. A pair of pulses forms a pulse pair if the second pulse ends within 5 clock ticks after the first one ends. The output X should go high for one clock tick at the end of every pulse pair. If a pulse is counted as part of one pulse pair, it is not also be counted as part of a subsequent pulse pair. That is, the circuit does not count overlapping pairs of pulses as separate pulse pairs. So, if the input is 0110 0101 0111 0, the output is 0000 0010 0000 1.
The state diagram shown below is for a state machine that implements a pulse pair detector. It uses a 3 bit counter, t. Complete the state diagram by filling in all the missing transitions and labeling all the transitions with appropriate conditions and actions.
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7. (15 points) The state diagram shown below is for a sequential circuit that counts the number periods where input A is less than or equal to input B for one or more time steps in a row (leRun), and the number of periods when A>B for at least two time steps in a row (gtRun). A and B are four bits each and there is an eight bit output X equal to leRun–gtRun. The circuit also has a reset signal which has been omitted from the diagram. When reset is high, the circuit should go to the start state and leRun and gtRun should both be set to 0.
Complete the VHDL module outlined on the next page so that it implements the sequential circuit specified by the state diagram. Include code for the reset and output X.
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entity countRuns is port ( clk, reset: in std_logic; A,B: in std_logic_vector(3 downto 0); X: out std_logic_vector(7 downto 0)); end countRuns; architecture a1 of countRuns is begin process ( ) begin end process; end a1;
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8. (8 points) For the state machine shown below, assume that the flip flop setup time is 2 ns, the hold time is 0.5 ns and the flip flop propagation delay is between 1 and 3 ns. Also, that the clock skew is 0.3 ns.
Is this circuit subject to internal hold time violations? Justify your answer.
What is the smallest clock period for which the circuit is not subject to setup time violations? Be sure to take into account any modifications from the previous step.
What is the latest time relative to the clock, when it is safe for input B to change?
What is the latest time after the clock when output X can be changing?