Other Flip Flops-Gates, Truth Tables and Digital Logic Design-Lecture Slides, Slides for Digital Logic Design. Punjab Engineering College

Digital Logic Design

Description: This course includes logic operators, gates, combinational and sequential circuits are studied along with their constituent elements comprising adders, decoders, encoders, multiplexers, as well as latches, flip-flops, counters and registers. This lecture includes: Other, Flip, Flop, Master, Slave, Arrangement, Timing, Diagram, J, K, T, Characteristic, Table, Equation, Response
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Overview of Last Lecture   

•  Difference between Latch and Flip Flop?  •  Latch is level sensi:ve  •  Flip Flop is edge sensi:ve 

•  Construc:on of Flip Flop  – Master Slave arrangement  – Using customized circuit 

•  Posi:ve Edge Triggered Flip Flop  •  Nega:ve Edge Triggered Flip Flop 


Quiz : Timing Diagram 


Today’s Lecture 

•  Other type of Flip Flops  •  JK Flip Flop  •  T Flip Flop 

– Characteris:c Table of Flip Flop?  – Characteris:c Equa:on of Flip Flop? 


Notes on Flip Flops

•  The timing of the response of a flip flop to input data and clock must be taken into consideration when using edge-triggered flip flops.

•  There is a minimum time, called setup time, for which the D input must be maintained at a constant value prior to the occurrence of the clock transition.

•  There is a minimum time, called hold time, for which the D input must not change after the application of the positive transition of the clock.

•  The propagation delay time of the flip flop is defined as the time interval between the trigger edge and the stabilization of the output to a new state.


Other Flip Flops

•  Other types of flip flops can be constructed by using the D flip flop and external logic. The two most commonly used are: –  JK flip flops –  T flip flops


JK Flip Flop

•  The JK flip flop performs three operations: –  set it to 1 –  reset it to 0 –  complement the output

•  The J input sets the flip flop to 1. •  The K input resets the flip flop to 0. •  When both J and K are enabled, the output

is complemented.


JK Flip Flop Logic


Analysis of the JK Circuit

•  The circuit applied to the D input is D = JQ’ + K’Q

–  If J = 1 and K = 0, D = Q + Q’ = 1, set to 1 –  If J = 0 and K = 1, D = 0, reset to 0 –  If J = K = 1, D = Q’, complements the output –  If J = K = 0, D = Q, leaving the output unchanged


JK Characteristic Table

Q(t+1) = J(t)Q’(t) + K’(t)Q(t)


T Flip Flop

•  The T (Toggle) flip flop is a complementing flip flop and can be obtained from a JK flip flop when inputs J and K are tied together.

•  The T flip flop can be obtained from a D flip flop by using an XOR as the input for D. –  The expression for D input is D = T ⊕ Q = TQ’ + T’Q –  When T = 0, ( j = k = 0 ) then D = Q and there is no change in the output –  When T = 1, ( j = k = 1 ) then D = Q’ and the output complements


T Flip Flop Logic


Characteristic Tables

•  Characteristic tables define the logical properties of a flip flop by describing its operations in tabular form. –  They define the next state as a function of the inputs and the present

state. –  Q(t) refers to the present state prior to the application of a clock edge. –  Q(t + 1) refers to the next state one clock period later. –  Clock edges are not listed as inputs but are implied by the transition from

t to t + 1.


T Flip Flop Characteristic Table


Characteristic Equations

•  The D flip flop can be expressed as: –  Q(t + 1) = D

•  The JK flip flop can be expressed as: –  Q(t + 1) = JQ’ + K’Q

•  The T flip flop can be expressed as: –  Q(t + 1) = TQ’ + T’Q


Direct Input to Flip Flops 


D Flip Flop with Asynchronous Reset 


Prac:ce Problem 

•  Make changes in circuits of  Master‐Slave D Flip  Flop with NAND Gates into D flip flop with Clear  and Preset inputs 




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