Power Inverters-Power Electronics and Inverter Design-Handout, Exercises of Power Electronics

Download Power Inverters-Power Electronics and Inverter Design-Handout and more Exercises Power Electronics in PDF only on Docsity! BWW 14 Power Inverters Inversion is the conversion of dc power to ac power at a desired output voltage or current and frequency. A static semiconductor inverter circuit performs this electrical energy inverting transformation. The terms voltage-fed and current-fed are used in connection with the output from inverter circuits. A voltage-source inverter (VSI) is one in which the dc input voltage is essentially constant and independent of the load current drawn. The inverter specifies the load voltage while the drawn current shape is dictated by the load. A current-source inverter (CSI) is one in which the source, hence the load current is predetermined and the load impedance determines the output voltage. The supply current cannot change quickly. This current is controlled by series dc supply inductance which prevents sudden changes in current. The load current magnitude is controlled by varying the input dc voltage to the large inductance, hence inverter response to load changes is slow. Being a current source, the inverter can survive an output short circuit thereby offering fault ride-through properties. Voltage control may be required to maintain a fixed output voltage when the dc input voltage regulation is poor, or to control power to a load. The inverter and its output can be single-phase, three-phase or multi-phase. Variable output frequency may be required for ac motor speed control where, in conjunc- tion with voltage or current control, constant motor flux can be maintained. Inverter output waveforms (either voltage or current) are usually rectilinear in nature and as such contain harmonics which may lead to reduced load efficiency and performance. Load harmonic reduction can be achieved by either filtering, selected harmonic-reduction chopping or pulse-width modulation. The quality of an inverter output is normally evaluated in terms of its harmonic factor, ρ, distortion factor, µ, and total harmonic distortion, thd. In section 12.6.2 these first two factors were defined in terms of the supply current. For VSI inverters the factors are redefined in terms of the output voltage harmonics as follows 1 1nn n V n n V ρ µ= = > (14.1) The distortion factor for an individual harmonic is 1 ρ µ = = nnn V nV n (14.2) 2 2 2 1 2 2 2 / ρ µ ∞ ∞ ∞ ≥ ≥ ≥     = = =           ∑ ∑ ∑n nn n n n V thd V n n (14.3) The factor Vn /n is used since the harmonic currents produced in an inductive load attenuate with frequency. The harmonic currents produce unwanted heating and torque oscillations in ac motors, although such harmonic currents are not a drawback to the power delivered to a resistive heating load or incandescent lighting load. 14.1 dc-to-ac voltage-source inverter bridge topologies 14.1.1 Single-phase voltage-source inverter bridge Figure 14.1a shows an H-bridge inverter (VSI) for producing an ac voltage and employing switches which may be transistors (MOSFET or IGBT), or at high powers, thyristors (GTO or GCT). Device conduction patterns are also shown in figures 14.1b and c. With inductive loads (not purely resistive), stored energy at turn-off is fed through the bridge reactive feedback or freewheel diodes D1 to D4. These four diodes clamp the load voltage to within the dc supply voltage rails (0 to Vs). Power Inverters 424 14.1.1i - Square-wave (bipolar) output Figure 14.1b shows waveforms for a square-wave output (2t1 = t2) where each device is turned on as appropriate for 180°, (that is π) of the output voltage cycle (state sequence 10, 01, 10, ..). The load current iL grows exponentially through T1 and T2 (state 10) according to (V)Ls L di V L i R dt = + (14.4) When T1 and T2 are turned off, T3 and T4 are turned on (state 01), thereby reversing the load voltage polarity. Because of the inductive nature of the load, the load current cannot reverse instantaneously and load reactive energy flows back into the supply via diodes D3 and D4 (which are in parallel with T3 and T4 respectively) according to (V)Ls L di V L i R dt − = + (14.5) The load current falls exponentially and at zero, T3 and T4 become forward-biased and conduct load current, thereby feeding power to the load. The output voltage is a square wave of magnitude ± Vs, figure 14.1b, and has an rms value of Vs. For a simple R-L load, with time constant τ = L /R, during the first cycle with no initial load current, solving equation (14.4) yields a load current ( ) 1 (A)τ − = −    s L tV i t e R (14.6) Under steady-state load conditions, the initial current is I ∨ as shown in figure 14.1b, and equation (14.4) yields 1 ( ) (A) 0 ½ (s) τ ∨ − = − −    ≤ ≤ = s s L tV V i t I e R R t t T (14.7) Figure 14.1. GCT thyristor single-phase bridge inverter: (a) circuit diagram; (b) square-wave output voltage; and (c) quasi-square-wave output voltage. I1 I ∧ I ∧ I ∨ o b a Vab T ½T ½T T α α +Vs -Vs δ½ 1 VL docsity.com Power Electronics 425 (V) 0 (A) ∨ = ≤ for L sv V I During the second half-cycle (t1 ≤ t ≤ t2) when the supply is effectively reversed across the load, equation (14.5) yields 1 2 1 ( ) 1 1 tanh (A) 2 0 ½ (s) τ τ τ − −∧      = − + + = − − +            ≤ ≤ − = t t s s s L V V V t i t I e e R R R t t t T (14.8) (V) 0 (A) ∧ = − ≥ for L sv V I A new time axis has been used in equation (14.8) starting at t = t1 in figure 14.1b. Since in steady-state by symmetry, -I I ∧ ∨ = , the initial steady-state current I ∧ can be found from equation (14.7) when, at t = t1, iL = I ∧ yielding 1 1 11- tanh (A) 21 t s s t V V te I I R R e τ τ τ − ∧ ∨ − −  = = =    + (14.9) The zero current cross-over point tx, shown on figure 14.1b, can be found by solving equation (14.7) for t = tx when iL = 0, which yields 1 1 (s) x s s I R t n V IR n V τ τ ∨   = −       = +     (14.10) The average thyristor current, TI , average diode current, DI , and mean source current, sI can be found by integration of the load current over the appropriated bounds. ( ) ( ) 1 1 2 1 2 1 1 x o t T L t t t s s o I i t dt t V V t t I e e t R R τ ττ − − =    = − + + −        ∫ (14.11) where iL is given by equation (14.7) and ( ) 0 2 2 1 1 1 x x t D L t s s x I i t dt t V V t I e t R R ττ − = −    = − − + −        ∫ (14.12) where iL is given by equation (14.8). Inspection of the source current waveform in figure 14.1b shows that the average dc voltage source current is related to the average semiconductor device currents by ( ) 1 1 2 2 1 1ττ − = −    = + + −        T Ds t s s I I I V V t I e t R R (14.13) The steady-state mean power delivered by the dc supply and absorbed by the resistive load component R is given by ( ) ( )1 2 0 1 1 (W)= = =∫ t sL s L s LrmstP V i dt V I I Rt (14.14) where iL(t) is given by equation (14.7). Rather than integration involving equations (14.7) and (14.8), the mean load power can be used to determine the rms load current: (A)= = s sLLrms V IPi R R (14.15) The rms output voltage is Vs and the output fundamental frequency fo is 1 21 1 1 2= = =o T ttf . Power Inverters 426 The instantaneous output voltage expressed as a Fourier series is given by 14 sin (V)ω π ∞ = ∑L s o n odd V V n t n (14.16) where 22 2 /o of tω π π= = and for n = 1 the magnitude of the fundament frequency fo is 4π sV which is an output rms fundamental voltage vo1 of 1 2 2 0.90 (V)o s sv V Vπ= = (14.17) The load current can be expressed in terms of the Fourier voltage waveform series, that is ( ) ( ) 1, 3, 5 1, 3, 5 4 1( ) sin sin ω ω φ π ω φ ∞ ∞ = = = − = − ∑ ∑ L s o n n n o n n n i t V n t nZ I n t (14.18) 2 2 1 1 1 rms 4 = = 2 ( ) tan such that cos π ωω φ φ−= + = = where whences nn n o n o n n V I I I nZ n L RZ R n L R Z The fundamental output power is 22 2 2 21 1 1 1 1 2 2 coso s v V P I R R Z R φ π    = = =         (14.19) The load power is given by the sum of each harmonic i2R power component, that is ( ) 2 2 1, 3, 5 1, 3, 5 2 ∞ ∞ = =  = = =   ∑ ∑ n sL sn rms n n IP R I R V I (14.20) Alternately, after integrating equation (14.14), with the load current from equation (14.8) 1 1 2 2 1 1 1 2 1 2 1 1 tanh 2 1 t s s L t V V teP R t R t e τ τ τ τ τ − −     − = − = −       +  (14.21) From PL = 2 rmsi R the rms loads current is 1 1 2 1 tanh 2 s L rms V t i R t τ τ   = −     (14.22) The load power factor is given by 2 1 1 2 1 tanh 2 L rsm L rms rms i R tPpf S i v t τ τ   = = = −     (14.23) 14.1.1ii - Quasi-square-wave (multilevel) output The rms output voltage form a H-bridge can be varied by producing a quasi-square output voltage (2t1 = t2, t0 < t1) as shown in figure 14.1c. After T1 and T2 have been turned on (state 10), at the angle α one device is turned off. If T1 is turned off (and T4 is turned on after a short delay), the load current slowly freewheels through T2 and D4 (state 00) in a zero voltage loop according to 0 (V)L L di L i R dt = + (14.24) When T2 is turned off and T3 turned on (state 01), the remaining load current rapidly reduces to zero back into the dc supply Vs, through diodes D3 and D4. When the load current reaches zero, T3 and T4 become forward biased and the output current reverses, through T3 and T4. The output voltage shown in figure 14.1c consists of a sequence of non-zero voltages ±Vs, alternated with zero output voltage periods. During the zero output voltage period a diode and switch conduct, firstly T1 and D3 in the first period, and T3 and D1 in the second zero output period. In each case, a zero voltage loop is formed by a switch, diode, and the load. The next two zero output sequences would be T2 and D4 then T4 and D2, forming alternating zero voltage loops (sequence 10, 00, 01, 11, 10, ..) rather than repeating a continuous T1 and D3 then T3 and D1 sequence of zero voltage loops (sequence 10, 11, 01, 11, 10, .. or sequence 10, 00, 01, 00, 10, ..). By alternating the zero voltage loops (between states 00 and 11), losses are uniformly distributed between the semiconductors, device switching frequency is half that experienced by the load, and a finer output voltage resolution is achievable. docsity.com Power Electronics 431 ii. The peak diode current is 25.9 A. The average diode current from equation (14.12) is 2.83ms 200 0 1 (34 - 59.9 ) 20ms = 1.66 A t DI e dt −= ∫ iii. The maximum blocking voltage of each device is 340 V dc. iv. The average supply current is ( ) ( )2 2 5.71A - 1.66A 8.10A= − = × =T DsI I I This results in the supply delivery power of 340Vdc × 8.10A = 2754W v. From equation (14.16), with the third as the lowest harmonic, the distortion factors are 3 133 1 1 , , 33 3ρ= = = that is per cent V hf V 33 1 1 , , 11.11 93 µ= = = that is per cent V df V vi. From equation (14.16) ( ) ( ) ( ) 2 1 2 2 21 1 1 3 5 7 / = ...... = 46.2  =     + + + ∑ per cent nVthd V n Quasi-square-wave, α = ½π (5 ms) and from equation (14.31) tx = 0.93ms i. The peak switch current is 18.9 A. From equation (14.32) the average switch current, using alternating zero volt loops, is 5ms 5ms -200 -200 0.93ms 0 1 1(34 - 41 ) 19 20ms 40ms = 2.18 + 1.50 = 3.68 A t t TI e dt e dt= +∫ ∫ ii. The peak diode current (and peak switch current) is 18.9 A. The average diode current, from equation (14.33), when using alternating zero volt loops, is given by ( ) 0.93ms 5ms 200 -200 0 0 1 134 41 19 20ms 40ms = 0.16 + 1.50 = 1.66 A t t DI e dt e dt −= − + +∫ ∫ iii. The maximum blocking voltage of each device type is 340 V. iv. The average supply current is ( ) ( )2 2 3.68A - 1.66A 4.04A= − = × =T DsI I I This results in the supply delivery power of 340Vdc × 4.04A = 1374W v. The harmonics are given by equations (14.1) to (14.3) 3 133 1 1 1 1/ 33 2 2 = , , 33 ρ= = = that is per cent V hf V 3 33 1 1 9 = = , , 11.11 ρµ= = that is per cent V df nnV vi. 2 1 2 2 2 2 2 1 / 1 1 1 ... = 46.2 3 5 7 9 ∞ ≥ −   =               = + + + +                ∑ per cent n n V thd V n ♣ Power Inverters 432 Example 14.2: Harmonic analysis of H-bridge inverter with an L-R load For each delay case (α = 0° and α = 90°) in example 14.1, using Fourier voltage analysis, determine (ignore harmonics above the 10th): i. the magnitude of the fundamental and first four harmonics ii. the load rms voltage and current iii. load power iv. load power factor Solution The appropriate harmonic analysis is outline in the following table, for α = 0° and α = 90°. n Zn Vn (α=0) In (α=0) Vn (α=90°) In (α=90°) harmonic ( )22 2 50R nLπ+ 0.9 sV n n n V Z ( ) 0.9 cos ½s V n n α n n V Z Ω V A V A 1 18.62 306 16.43 216.37 11.62 3 48.17 102 2.12 -72.12 -1.50 5 79.17 61.2 0.77 -43.28 -0.55 7 110.41 43.71 0.40 30.91 0.28 9 141.72 34 0.24 24.04 0.17 332.95V 16.59A 235.43V 11.73A i. The magnitude of the fundamental voltage is 306V for the square wave and is reduced to 216V when a phase delay angle of 90° is introduced. The table shows that the harmonics magnitudes reduce ( )1n as the harmonic order increases. ii. The rms load current and voltage can be derived by the square root of the sum of the squares of the fundamental and harmonic components, that is, for the current 2 2 21 3 5 .....rmsi I I I= + + + The load rms currents, from the table, are 16.59A and 11.73A, which agree with the values obtained in example 14.1a. Notice that the predicted rms voltages of 333V and 235V differ significantly from the values in example 14.1a, given by 1 απ−sV , namely 340V and 240.4V respectively. This is because the magnitude of the harmonics higher in order than 10 are not insignificant. The error introduced into the rms current value by ignoring these higher order voltages is insignificant because the impedance increases approximately proportionally with harmonic number, hence the resultant current becomes much smaller (insignificant) as the order increases. iii. The load power is the load i2R loss, that is 2 2 2 2 16.59 10 2752W 0 11.73 10 1376W 90 α α = = × Ω = = = = × Ω = = ° for for L rms L rms P i R P i R iv. The load power factor is the ratio of real power dissipated to apparent power, that is 2 2 2752W 0.488 0 16.59A 340V 1376W 0.486 90 11.79A 240.4V α α = = = = = × = = = = = ° × for for rms rms rms rms rms rms i RP pf S i v i RP pf S i v Equations (14.23) and (14.44) confirm the load power factor is 0.488, independent of α. ♣ Example 14.3: Single-phase half-bridge inverter with an L-R load A single-phase half-bridge inverter as shown in the figure 14.3, supplies a 10 ohm resistance with inductance 50 mH from a 340 V dc source. If the bridge is operating at 50 Hz, determine for the square- wave output i. steady-state current waveforms ii. the load rms voltage iii. the peak load current and its time domain solution, iL(t) docsity.com Power Electronics 433 (a) (b) (c) Clower Cupper Cl Cu Cl Cl Cu I ∨ tx ½Vs ½Vs ½Vs ½Vs 170V -170V 12.95A -12.95A 2.83ms +½Vs -½Vs δ½ 1 VL I ∧ t1 t2 + + iv. the average and peak current in the switches v. the average and peak current in the diodes vi. the peak blocking voltage of each semiconductor type vii. the power delivered to the load, rms load current, and average supply current Figure 14.3. GCT thyristor single-phase half-bridge inverter: (a) circuit diagram; (b) square-wave output voltage; and (c) output voltage transfer function. Solution From examples 14.1 and 14.2, τ = 5ms. i. Figure 14.3 shows the output voltage and current waveforms, with various circuit component current waveforms superimposed. Note that no zero voltage loops can be created with the half-bridge. Only load voltages ±½Vs , that is ±170V dc, are possible. ii. The output voltage swing is ±½Vs, ±170V, thus the rms output voltage is ½Vs, 170V. This is, half that of the full-bridge inverter using the same magnitude source voltage Vs, 340V dc. iii. The peak load current is half that given by equation (14.9), that is 1 1 1½ ½1 tanh 21 ½×340V 10ms= × tanh 12.95A 10Ω 2×5ms t s s t V V te I R R e τ τ τ − ∧ − −  = =    +   =    The load current waveform is defined by equations (14.7) and (14.8), specifically 5ms 5ms ½ ½ ( ) ½ 340V ½ 340V 12.95A 10 10 17 29.95 0 10ms τ −∨ − −  = − − ×    × × = − + × Ω Ω  = − ≤ ≤for I t s s L t t V V i t I e R R e e t and 5ms 5ms ½ ½ ( ) ½×340V ½×340V 12.95 10Ω 10Ω 17 29.95 0 10ms τ −∧ − −  = − + + ×     = − + + ×    = − + ≤ ≤for II t s s L t t V V i t I e R R e e t By halving the effective supply voltage, the current swing is also halved. iv. The peak switch current is 12 95I = . A . The average switch current is given by 10ms 5ms 2.83ms 1 (17 29.95 ) 20ms = 2.86 A t TI e dt − = −∫ v. The peak diode current is = 12.95AI . Power Inverters 434 The average diode current is given by 2.83ms 5ms 0 1 17 29.95 20ms = 0.83 A t DI e dt − = −   ∫ vi. When a switch or diode of a parallel pair conduct, the complementary pair of devices experience a voltage Vs, 340V dc. Thus although the load experiences half the supply voltage, the semiconductors experience twice that voltage, the same voltage experienced by the switches in the full bridge inverter. vii. The load power (whence various currents) is found by averaging the instantaneous load power ( ) 10 s -200t 0 1 170V 17 - 29.95 e 10ms 638.5W 638.5W= 638.5 W 8A 1.88A10Ω 340V = × × = = = = = = ∫ m L L L rms s s P PP dt i IR V ♣ 14.1.1iii - PWM-wave output The output voltage and frequency of a single-phase voltage- source inverter bridge can be control using one of two forms of pulse-width modulation, termed: • bipolar • multi-level, usually called unipolar Both pwm techniques have been analysed extensively for dc voltage outputs when applied to the two quadrant and four quadrant dc choppers considered in Chapter 13, sections 13.5 and 13.6. It will be seen that the same triangular modulation principles can be applied and extended, when producing low- harmonic single-phase ac output voltages and currents. The main voltage output difference between the two methods is the harmonic content near the carrier frequency and its harmonics. Three-phase pwm is a naturally extension to the single-phase case, except single-phase pwm offers more degrees of flexibility than its application to three phase inverters, although three-phase pwm does have the attribute of triplen harmonic cancellation, due to the use of one (co-phasal) triangular carrier. Figure 14.4. Bipolar pulse width modulation: (a) carrier and modulation waveforms and (b) resultant load pwm waveform. Bipolar pulse width modulation Bipolar modulation is the simplest pwm method and involves comparing a fixed frequency and magnitude triangular carrier with the ac waveform desired, called the modulation waveform. The modulation is usually a sinusoid of magnitude (modulation index) M such that 0 ≤ M ≤ 1. +1 -1 M V∆ Vref Vs -Vs T1 T2 ON T1 T2 ON T1 T2 ON T3 T4 ON T3 T4 ON T3 T4 ON T1 T2 ON T1 T2 ON T3 T4 ON T3 T4 ON VL (a) (b) docsity.com Power Electronics 435 The waveforms in figure 14.4 shown that the load voltage VL swings between the two voltage levels, +Vs and -Vs, (hence the term bipolar output voltage), according to • T1 and T2 are on when vref > v∆ (T3 and T4 are off ) such that VL = +Vs • T3 and T4 are on when vref < v∆ (T1 and T2 are off ) such that VL = -Vs Multi-level pulse width modulation Two multilevel output voltage techniques can be use with single-phase voltage fed ac bridges. In both case, two triangular carries displaced by 180° give the same output for the same switching frequency. i. The waveforms in figure 14.5 show that the load voltage VL swings between the two voltage levels, +Vs and -Vs, with interspaced zero periods (hence the term multilevel, specifically three-level in this case, 0V and ±Vs ), according to • T1 is on when vref > v∆ such that Vao = +Vs • T4 is on when vref < v∆ such that Vao = 0V • T3 is on when vref < -v∆ such that Vbo = Vs • T2 is on when vref > -v∆ such that Vbo = 0V The multilevel load output voltage is the difference between the two leg voltage waveforms and can be defines as follows: • T1 and T2 are on such that Vao = +Vs, Vbo = 0V, Vab = +Vs • T2 and T3 are on such that Vao = 0V, Vbo = +Vs, Vab = -Vs • T1 and T3 are on such that Vao = +Vs, Vbo = +Vs, Vab = 0V • T2 and T4 are on such that Vao = 0V, Vbo = 0V, Vab = 0V The two zero output states are interleaved to balance switching losses between all four bridge switches. Device switching is at the carrier frequency, but the bridge load voltage (hence load current) experiences twice the leg switching frequency since the two carriers are displaced by 180°. ii. A second multilevel output voltage approach is shown in figure 14.15, where the triangular carriers are not only displaced by 180° in time, but are vertically displaced, as for multilevel inverter pwm generation, which is considered in section 14.4. The upper triangle modulates reference values greater than zero, while the lower triangle modulates when the reference is less than zero. Figure 14.5. Multilevel (3 level) pulse width modulation: (a) carriers and modulation waveforms and (b) resultant load pwm waveforms. Vref Vab VL +1 -1 M V∆ Vs -Vs -V∆ Vs Vs Vbo Vao (a) (b) Vab=Vao-Vbo T1 on (T4 off) T4 on (T1 off) T3 on (T2 off) T2 on (T3 off) Power Inverters 436 with single-phase multilevel pwm nfc = 0 for all n (suppressed carrier) fo 1×fc 2×fc 3×fc 4×fc M - 2 fo 2fc- fo 2fc+ fo 2fc-3fo 2fc+3fo 2 fo fo 1×fc 2×fc 3×fc 4×fc M - with single-phase bipolar pwm nfc = 0 for n even 2fc- fo 2fc+ fo 2fc-3fo 2fc+3fo fc fc- 2fo fc+ 2fo fc- 4fo fc+ 4fo (a) (b) Spectral comparison between bipolar and multilevel pwm waveforms The key features of the H-bridge inverter output voltage with bipolar pwm are (fig 14.6a): • a triangular carrier has only odd Fourier components, so the output spectrum only has carrier components at odd harmonics of the carrier frequency • the first carrier components occur at the carrier frequency, fc • side-band components occur spaced by 2fo from other components, around all multiples of the carrier frequency fc From figure 14.6b, the key features of the H-bridge inverter output voltage with multilevel pwm are: • the output switching frequency is double 2fc each leg switching frequency fc, since the switching of each leg is time shifted (by 180°), hence the first carrier related components in the output occur at 2fc and then at multiples of 2fc • no triangular carrier Fourier components exist in the output voltage since the two carriers are in anti-phase (180° apart), effectively cancelling one another in spectrum terms • side-band components occur spaced by 2fo from other components, around each multiple of the carrier frequency 2fc Figure 14.6. Typical phase output frequency spectrum, at a give switch commutation frequency, for: (a) bipolar pwm and (b) multilevel pwm. 14.1.2 Three-phase voltage-source inverter bridge The basic dc to three-phase voltage-source inverter (VSI) bridge is shown in figure 14.7. It comprises six power switches together with six associated reactive energy feedback diodes. Each of the three inverter legs operates at a relative time displacement (phase) of ⅔π, 120°. Table 14.1. Quasi-square-wave six conduction states - 180° conduction. Interval Three conducting switches leg state voltage vector 1 T1 T2 T3 101 v5 2 T2 T3 T4 001 v1 3 T3 T4 T5 011 v3 4 T4 T5 T6 010 v2 5 T5 T6 T1 110 v6 6 T6 T1 T2 100 v4 docsity.com Power Electronics 441 Figure 14.8b for 180° conduction and 14.11b for 120° conduction show that the line to neutral voltage of one conduction pattern is proportional to the line-to-line voltage of the other. That is, from equation (14.38) with α = ⅓π ( ) ( ) [ ] 2 3 1,3,5 1 1 1 5 7 11 2½ cos sin 6 3 sin - sin 5 - sin 7 sin11 + . . . (V) ππ π ω π ω ω ω ωπ ∞ = = = = + ∑RN RY s n s n v v V n t n V t t t t (14.51) and ( ) ( ) [ ] 2 3 1,3,5 3 2 1 1 1 5 7 11 2 3 cos sin 6 3 sin sin 5 sin 7 sin11 + . . . (V) ππ π ω π ω ω ω ωπ ∞ = = = = + + + ∑RY RN s n s n v v V n t n V t t t t (14.52) Also vRY = √3 vRN and the phase relationship between these line and phase voltages, of π, has not been retained. That is, with respect to figure 14.11b, substitute ωt with ωt + π in equation (14.51) and ωt + ⅓π in equation (14.52). The output voltage properties for both 120° and 180° conduction are summarised in the Table 14.2. Table 14.3. Quasi-squarewave conduction states - 120° conduction. Interval Two conducting devices 1 T1 T2 2 T2 T3 3 T3 T4 4 T4 T5 5 T5 T6 6 T6 T1 Independent of the conduction angle (120°, 180° or even 150°), quasi-square 180° conduction occurs with inductive loads, producing the six hexagon states shown in the upper part of figure 14.10. The resistive load assumptions made in this section for explanation purposes can be misleading. 14.1.3 Inverter ac output voltage and frequency control techniques It is a common requirement that the output voltage and/or frequency of an inverter be varied in order to control the load power or, in the case of an induction motor, to control the shaft speed and torque by maintaining a constant V / f ratio. The six VSI modulation control techniques to be considered are: • Variable voltage dc link • Single-pulse width modulation • Multi-pulse width modulation • Multi-pulse, selected notching modulation • Sinusoidal pulse width modulation • Triplen injection Triplens injected into the modulation waveform Voltage space vector modulation 14.1.3i - Variable voltage dc link The rms voltage of a square-wave can be changed and controlled by varying the dc link source voltage. A variable dc link voltage can be achieved with a dc chopper as considered in chapter 13 or an ac phase-controlled thyristor bridge as considered in sections 11.2 and 11.5. A dc link L-C smoothing filter may be necessary. 14.1.3ii - Single-pulse width modulation Simple pulse-width control can be employed as considered in section 14.1.1b, where a single-phase bridge is used to produce a quasi-square-wave output voltage as shown in figure 14.1c. An alternative method of producing a quasi-square wave of controllable pulse width is to transformer- add the square-wave outputs from two push-pull bridge inverters as shown in figure 14.12a. By phase- shifting the output by α, a quasi-square sum results as shown in figure 14.12b. Power Inverters 442 Figure 14.11. A three-phase bridge inverter employing 120° switch conduction with a resistive star load: (a) the bridge circuit showing T1 and T2 conducting; (b) circuit voltage and current waveforms; and (c) phase voltage to line voltage conversion matrix. The output voltage can be described by sin (V)o an n odd V v n tω ∞ = ∑ (14.53) where ½ ½ 42 cos cos(½ ) (V)an s sv V n d V nn π π α α απ π−= =∫ (14.54) The rms output voltage is 1- (V)r sV V απ= (14.55) 1 -1 0 0 1 -1 -1 0 1 RB RN BN BY BN YN YR YN RN RN BN YN v v v v v v v v v v v v −        = −       −         =           (c) docsity.com Power Electronics 443 and the rms value of the fundamental is 1 2 2 cos½ (V)sV V απ = (14.56) As α increases, the magnitude of the harmonics, particularly the third, becomes significant compared with the fundamental magnitude. This type of control may be used in high power applications. Figure 14.12. Voltage control by combining phase-shifted push-pull inverters: (a) two inverters with two transformers for summing and (b) circuit voltage waveforms for a phase displacement of α. Example 14.4: Single-pulse width modulation Two single-phase H-bridge inverter outputs are transformer added, as shown in figure 14.12. Each inverter operates at 50Hz but phase shifted so as to produce 240V rms fundamental output when the rail voltage of each inverter is 340V dc and the transformers turns ratios are 2:2:1. Determine i. the phase shift between the two single phase inverters ii. the rms output voltage iii. the frequency and magnitude of the first 4 harmonics of 50Hz and their rms ac contribution to the rms output iv. rms voltage of higher order harmonics (higher frequencies than those in part iii.) v. the total harmonic distortion of the output voltage. Solution i. The output is a quasi-square waveform of magnitude ±340V dc. The magnitude of the 50Hz fundamental is given by equation (14.54), for n =1: 1 4 cos(½ ) 42 240V 340V cos(½ ) a sv V απ απ = = × × from which the phase shift is 76.7°, 1.34 radians. Power Inverters 444 ii. The rms output voltage is given by equation (14.55), that is 1.34 1- 340V 1- 257.5Vrms sV V α π π= = = iii. The peak values of the first four harmonics are given in the table below. harmonic n 4 cos(½ ) an sv V nn απ= 2 anv 3 -61.4 3765.0 5 -84.7 7175.3 7 -1.4 1.9 9 46.6 2168.5 . 2 anv =∑ 114.50 The rms value of the ac of the first four harmonics is 114.5/√2 = 81.0V. iv. The ac component of the harmonics above the 9th is given by ( ) 2 2 9 9 2 2 2257.5V 240V 81.0V 46.3V rms n rms rms nV V V> ≤= − = − + = v. The total harmonic voltage distortion is given by 1 22 2 1 1 2 100 1 100 257.5V 1 100 38.9% 240V −   = × = − ×     = − × =    rms a rms v a a V V V THD V V ♣ 14.1.3iii - Multi-pulse width modulation An extension of the single-pulse modulation technique is multiple-notching as shown in figure 14.13. The bridge switches are controlled so as to vary the on to off time of each notch, δ, thereby varying the output rms voltage which is given by rms sV Vδ= . Alternatively, the number of notches can be varied. Figure 14.13. Inverter control giving variable duty cycle of five notches per half cycle: (a) low duty cycle, δ1, hence low fundamental magnitude and (b) higher duty cycle, δ2, for a high fundamental voltage output. +Vs -Vs +Vs -Vs δ1 δ2 δ1 < δ2 fo fo Carrier frequency fc docsity.com Power Electronics 445 The harmonic content at lower output voltages is significantly lower than that obtained with single-pulse modulation. The increased switching frequency does increase the magnitude of higher order harmonics and the switching losses. The Fourier coefficients of the output voltage in figure 14.13 are given by ( ) ( ) 1,2,3,.. 4 cos 2 2 1 cos 2 2 1 fc fo o o n j c c f f V n j n j n f f π δ π δ π =   = − + − − −    ∑ (14.57) where fo is the fundamental frequency, fc the triangular carrier frequency and 0 ≤ δ ≤ 1 is the duty cycle. 14.1.3iv - Multi-pulse, selected notching modulation If a multi-level waveform (±Vs, 0) is used with quarter wave symmetry, as shown in figure 14.14a, then both the harmonics and total rms output voltage can be controlled. With one pulse per quarter wave, the kth harmonic is eliminated from the output voltage if the centre of the pulse is located such that sin 0 that is k k λ πλ = = (14.58) Independent of the pulse width δ, the kth harmonic is eliminated and the other Fourier components are given by 8 sin sinn sV V n nn k π δ π = (14.59) The output voltage total rms is solely dependent on the pulse width δ and is given by 2o rms sV V δπ = (14.60) On the other hand, the bipolar waveform (±Vs) in figure 14.14b has an rms value of Vs, independent of the harmonics eliminated. Selected elimination of lower-order harmonics can be achieved by producing an output voltage waveform as shown in figure 14.14b. The exact switching points are calculated off-line so as to eliminate the required harmonics. For n switchings per half cycle, n selected harmonics can be eliminated. Figure 14.14. Output voltage harmonic reduction for a single-phase bridge using selected notching: (a) multilevel output voltage and (b) bipolar output voltage. λ λ δ Vs -Vs π 2π ½π vL ωt (a) (b) λ δ 1 1 1 1 Power Inverters 446 In figure 14.14b two notches per half cycle are introduced; hence any two selected harmonics can be eliminated. The more notches, the lower is the output fundamental. For example, with two notches, the third and fifth harmonics are eliminated. From ( ) ½ 0 4 sin 1, 2, 3, .... π π θ θ θ= =∫ fornb f n d n (14.61) ( ) ( ) 3 5 4 1 2cos3 2cos3 0 3 4 1 2cos5 2cos5 0 5 α β π α β π = − + = = − + = and s s b V b V Solving yields α1 = 23.6° and β1 = 33.3°. The total rms output voltage is Vs, independent of the harmonics eliminated. The magnitude (whence rms) of each harmonic component is ( )4 1 4 sin sinn sV V n nn λ δπ= − × × (14.62) The maximum fundamental rms component of the output voltage waveform is 0.84 of a square wave, which is (2√2/π)Vs when δ = ½π which produces a square wave. Ten switching intervals exist compared with two per cycle for a squarewave, hence switching losses and control circuit complexity are increased. In the case of a three-phase inverter bridge, the third harmonic does not exist, hence the fifth and seventh (b5 and b7) can be eliminated with α1 = 16.3° and β1 = 22.1. The 5th, 7th, 11 th, and 13th can be eliminated with the angles 10.55°, 16.09°, 30.91°, and 32.87° respectively. Because the waveforms have quarter wave symmetry, only angles for 90° need be stored. The output rms voltage magnitude can be varied by controlling the dc link voltage or by transformer- adding two phase-displaced bridge outputs as demonstrated in figure 14.12. The output voltage Fourier components in equation (14.62) are modified by equation(14.54) given ( ) ½4 1 4 sin sin cosn sV V n n nn λ δ απ= − × × (14.63) And the total rms output voltage is reduced from Vs , as given by equation (14.55), that is 1 - (V)o rms sV V α π= (14.64) Thus the fundamental rms magnitude can be changed by introducing an extra constraint to be satisfied, along with the harmonic eliminating constraints (as a result of the extra constraint, one fewer harmonic can now be eliminated for a given number of switchings per quarter cycle). The multi-pulse selected notching modulation technique can be extended to the optimal pulse-width modulation method, where harmonics may not be eliminated, but minimised according to a specific criterion. In this method, the quarter wave output is considered to have a number of switching angles. These angles are selected so as, for example, to eliminate certain harmonics, minimise the rms of the ripple current, or any other desired performance index. The resultant non-linear equations are solved using numerical methods off-line. The computed angles are then stored in a ROM look-up table for use. A set of angles must be computed and stored for each desired level of the voltage fundamental and output frequency. The optimal pwm approach is particularly useful for high-power, high-voltage GCT thyristor inverters, which tend to be limited in switching frequency by device switching losses. 14.1.3v - Sinusoidal pulse-width modulation (pwm) 1 - Natural sampling (a) Synchronous carrier The output voltage waveform and method of generation for synchronous carrier, natural sampling sinusoidal pwm, suitable for the single-phase bridge of figure 14.1, are illustrated in figure 14.15. The switching points are determined by the intersection of the triangular carrier wave fc and the reference modulation sine wave, fo. The output frequency is at the sine-wave frequency fo and the output voltage is proportional to the magnitude of the sine wave. The amplitude M (0 ≤ M ≤ 1) is called the modulation index. For example, figure 14.15a shows maximum voltage output (M = 1), while in figure 14.15b where the sine-wave magnitude is halved (M = 0.5), the output voltage is halved. If the frequency of the modulation sinewave, fo, is an integer multiple of the triangular wave carrier- frequency, fc that is, fc = nfo where n is integer, then the modulation is synchronous, as shown in figure docsity.com Power Electronics 451 fo 1 fc 2 fc 3 fc 4 fc M - 2fo 2fo with single-phase unipolar pwm fh = 0 for n odd (suppressed carrier and n - odd side bands) 3 - Frequency spectra of pwm waveforms The most common form of sinusoidal modulation for three-phase inverters is regular sampling, asynchronous, fixed frequency carrier, pwm. If fc > 20fo, low frequency subharmonics can be ignored. The output spectra consists of the modulation frequency fo with magnitude M. Also present are the spectra components associated with the triangular carrier, fc. For any sampling, these are fc and the odd harmonics of fc. (The triangular carrier fc contains only odd harmonics). These decrease in magnitude with increasing frequency. About the frequency nfc are components of fo spaced at ± 2fo, which generally decrease in magnitude when further away from nfc. That is, at fc the harmonics present are fc, fc ± 2fo, fc ± 4fo, … while about 2fc, the harmonics present are 2fc ± f0, 2fc ± 3fo,..., but 2fc is not present. The typical output spectrum is shown in figure 14.19. The relative magnitudes of the sidebands vary with modulation depth and the carrier related frequencies present, fh, are given by ( )( ) ( )( )( )1½ 1 1 2 ½ 1 1+= + − ± − + −n nh c of n f k f (14.69) 1, 2, 3,.... ( ) 1, 2, 3,.... ( )= =where sidebands and carrierk n Figure 14.19. Location of carrier harmonics and modulation frequency sidebands, showing all sideband separated by 2fm. Although the various pwm techniques produce other less predominate spectra components, the main difference is seen in the magnitude of the carrier harmonics and sidebands. The magnitudes increase as the pwm type changes from naturally sampling to regular sampling, then from asymmetrical to sym- metrical modulation, and finally from double edge to single edge. With a three-phase inverter, the carrier fc and its harmonics do not appear in the line-to-line voltages since the carrier fc and in particular its harmonics, are co-phase to the three modulation waveforms. 14.1.3vi - Phase dead-banding Dead banding is when one phase (leg) is in a fixed on state, and the remaining phases are appropriately modulated so that the phase currents remain sinusoidal. The dead banding occurs for 60° periods of each cycle with the phase with the largest magnitude voltage being permanently turned on. Sequentially each switch is clamped to the appropriate link rail. The leg output is in a high state if it is associated with the largest positive phase voltage magnitude, while the phase output is zero if it is associated with the largest negative phase magnitude. Thus the phase outputs are cycled, being alternately clamped high and low for 60° every 180° as shown in figure 14.20. A consequence of dead banding is reduced switching losses since each leg is not switched at the carrier frequency for 120° (two 60° periods 180° apart). A consequence of dead banding is increased ripple current. Dead banding is achieved with discontinuous modulating reference signals. Dead banding for a continuous 120° per phase leg is also possible but the switching loss savings are not uniformly distributed amongst the six inverter switches. The magnitude of the fundamental when using standard PWM can be increased from 0.827pu to 0.955pu without introducing output voltage distortion, by the injection of triplen components, which are co-phasal in a three-phase system, and therefore do not appear in the line currents. Two basic approaches can be used to affect this undistorted output voltage magnitude increase. Triplen injection into the modulation waveform or Voltage space vector modulation Power Inverters 452 o 1 π 3 2 π 3 π 4 π 3 5 π 3 2π ω t m = 0 m = ¼ m = ½ m = ¾ m = 1 Figure 14.20. Modulation reference waveform for phase dead banding. 14.1.3vii - Triplen Injection modulation 1 - Triplens injected into the modulation waveform An inverter reconstitutes three-phase voltages with a maximum magnitude of 0.827 (3√3/2π) of the fixed three-phase input ac supply. A motor designed for the fixed mains supply is therefore under-fluxed at rated frequency and not fully utilised on an inverter. As will be shown, by using third harmonic voltage injection, the flux level can be increased to 0.955 (3/π) of that produced on the three-phase ac mains supply. If overmodulation (M > 1) is not allowed, then the modulation wave M sin ωt is restricted in magnitude to M = 1, as shown in figure 14.21a. If VRN = M sinωt ≤ 1pu and VYN = M sin(ωt + ⅔π) ≤ 1 pu then VRY = √3 M sin(ωt - π) where 0 ≤ M ≤ 1 In a three-phase pwm generator, the fact that harmonics at 3fo (and odd multiplies of 3fo) vectorally cancel can be utilised effectively to increase M beyond 1, yet still ensure modulation occurs for every carrier frequency cycle. Let VRN = M′ sinωt+ sin3ωt) ≤ 1 pu and VYN = M′ ( sin(ωt +⅔π) +  sin 3(ωt + ⅔π)) ≤ 1 pu then VRY = √3 M′ sin(ωt - π) VRN has a maximum instantaneous value of 1 pu at ωt = ±⅓π, as shown in figure 14.21b. Therefore ( )13 3 ' 1 2RN V t Mω π= = = that is 2' 1.155 3 M M M= = (14.70) Thus the fundamental of the phase voltage is M′ sin ωt = 1.155 M sin ωt. That is, if the modulation reference sin ωt +  sin 3ωt is used, the fundamental output voltage is 15.5 per cent larger than when sin ωt is used as a reference. The increased fundamental is shown in figure 14.21b. docsity.com Power Electronics 453 Figure 14.21. Modulation reference waveforms: (a) sinusoidal reference, sin ωt; (b) third harmonic injection reference, sin ωt +  sin 3ωt; and (c) triplen injection reference, sin ωt + (1/√3π){9/8 sin3ωt - 80/81 sin9ωt + . ..} where the near triangular waveform b is half the magnitude of the shaded area. The spatial voltage vector technique injects the triplens according to ( ) ( ) ( ) ( ) 0 1 1 3 3 11' sin sin 2 1 3 2 1 2 13RN r r V M t r t r r ω ω π ∞ = −    = + +      + − + +      ∑ (14.71) The Fourier triplen series represents half the magnitude of the shaded area in figure 14.21c (the waveform marked ‘b’), which is formed by the three-phase sinusoidal waveforms. The spatial voltage vector waveform is defined by 1 6 1 1 6 6 3 sin( ) 0 2 3 sin( ) ½ 2 t t t t ω ω π ω π π ω π ≤ ≤ + ≤ ≤ (14.72) The use of this reference increases the duration of the zero volt loops, thereby decreasing inverter output current ripple. The maximum modulation index is 1.155. Third harmonic injection, yielding M = 1.155, is a satisfactory approximation to spatial voltage vector injection. 2 - Voltage space vector pwm When generating three-phase quasi-square output voltages, the inverter switches step progressively to each of the six switch output possibilities (states). In figure 14.10, when producing the quasi-square output, each of these six states is represented by an output voltage space vector. Each vector has a ⅓π displacement from its two adjacent states, and each has a length Vs which is the pole output voltage relative to the inverter 0V rail. Effectively, the quasi-square three-phase output is generated by a rotating vector of length Vs, jumping successively from one output state to the next in the sequence, and in so doing creating six voltage output sectors. The speed of rotation, in particular the time for one ×1.155 Power Inverters 454 rotation, determines the inverter output frequency. The sequence of voltage vectors {v1, v3, v2, v6, v4, v5} is arranged such that stepping from one state to the next involves only one of the three poles changing state. Thus the number of inverter devices needing to change states (switch) at each transition, is minimised. [If the inverter switches are relabelled, upper switches T1, T2, T3 - right to left; and lower switches T4, T5, T6 - right to left: then the rotating voltage sequence becomes {v1, v2, v3, v4, v5, v6}] Rather than stepping ⅓π radians per step, from one voltage space vector position to the next, thereby producing a six-step quasi-square fixed magnitude voltage output, the rotating vector is rotated in smaller steps based on the position being updated at a constant rate (carrier frequency). Furthermore, the vector length can be varied, modulated, to a magnitude less than Vs. ( )13/ 1 / 1 3 3 2 sin 3 2 sin 3 π θ θ − = = = = =where o p aa c s o p bb c s V Vt T v V V Vt v v T v V (14.73) Figure 14.22. Instantaneous output voltage states for the three legs of an inverter. 0 0 1 v1 0 1 1 v3 0 1 0 v2 1 1 0 v6 1 0 0 v4 1 0 1 v5 1 1 1 v7 0 0 0 v0 0 0 0 1 1 1 SECTOR II SECTOR III SECTOR IV SECTOR V SECTOR VI SECTOR I Interval # 1 T1 T2 T3 on leg state 101 v5 = Vs e -π j Interval # 2 T2 T3 T4 on leg state 001 v1 = Vs e 0 j Interval # 3 T3 T4 T5 on leg state 011 v3 = Vs e π j Interval # 4 T4 T5 T6 on leg state 010 v2 = Vs e π j Interval # 5 T1 T5 T6 on leg state 110 v6 = Vs e π j Interval # 6 T1 T2 T6 on leg state 100 v4 = Vs e  π j docsity.com Power Electronics 455 To incorporate a variable rotating vector length (modulation depth), it is necessary to vary the average voltage in each carrier period. Hence pulse width modulation is used in the period between each finite step of the rotating vector. Pulse width modulation requires the introduction of zero voltage output states, namely all the top switches on (state 111, v7) or all the lower switches on (state 000, v0). These two extra states are shown in figure 14.22, at the centre of the hexagon. Now the pole-to-pole output voltage can be zero, which allows duty cycle variation to achieve variable average output voltage for each phase, within each carrier period, proportional to the magnitude of the position vector. To facilitate vector positions (angles) that do not lie on one of the six quasi-square output vectors, an intermediate vector Vo/p e jθ is resolved into the vector sum of the two quasi-square vectors adjacent to the rotating vector. This process is shown in figure 14.23 for a voltage vector Vo/p that lies in sector I, between output states v1 (001) and v3 (011). The voltage vector has been resolved into the two components Va and Vb as shown. The time represented by quasi-square vectors v1 and v3 is the carrier period Tc, in each case. Therefore the portion of Tc associated with va and vb is scaled proportionally to v1 and v3, giving ta and tb. The two sine terms in equation (14.73) generate two sine waves displaced by 120°, identical to that generated with standard carrier based sinusoidal pwm. The sum of ta and tb cannot be greater than the carrier period Tc, thus a b c a b o c t t T t t t T + ≤ + + = (14.74) where the slack variable to has been included to form an equality. The equality dictates that vector v1 is used for a period ta, v3 is used for a period tb, and during period to, the null vector, v0 or v7, at the centre of the hexagon is used, which do not affect the average voltage during the carrier interval Tc. A further constraint is imposed in the time domain. The rotating voltage vector is a fixed length for all rotating angles, for a given inverter output voltage. Its length is restricted in both time and space. Obviously the resolved component lengths cannot exceed the pole vector length, Vs. Additionally, the two vector magnitudes are each a portion of the carrier period, where ta and tb could be both equal to Tc, that is, they both have a maximum length Vs. The anomaly is that voltages va and vb are added vectorially but their scalar durations (times ta and tb) are added linearly. The longest time ta + tb possible is when to is zero, as shown in figures 14.23a and 14.22a, by the hexagon boundary. The shortest vector to the boundary is where both resolving vectors have a length ½Vs, as shown in figure 14.23b. For such a condition, ta = tb = ½Tc, that is ta + tb = Tc. Thus for a constant inverter output voltage, when the rotating voltage vector has a constant length, / ,o pV the locus of allowable rotating reference voltage vectors must be within the circle scribed by the maximum length vector shown in figure 14.23b. As shown, this vector has a length v1 cos30°, specifically 0.866Vs. Thus the full quasi-square vectors v1, v2, etc., which have a magnitude of 1×Vs, cannot be used for generating a sinusoidal output voltage. The excess length of each quasi-square voltage (which represents time) is accounted for by using zero state voltage vectors for a period corresponding to that extra length (1- cos 30° at maximum output voltage). Having calculated the necessary periods for the inverter poles (ta, tb, and to), the carrier period switching pattern can be assigned in two ways. • Minimised current ripple • Minimised switching losses, using dead banding Each approach is shown in figure 14.24, using single edged modulation. The waveforms are based on the equivalent of symmetrical modulation where the pulses are symmetrical about the carrier trough. By minimising the current ripple, seven switching states are used per carrier cycle, while for loss minimisation (dead banding) only five switching states occur, but at the expense of increased ripple current in the output current. When dead banding, the zero voltage state v0 is used in even numbered sextants and v7 is used in odd numbered sextants. Sideband and harmonic component magnitudes can be decreased if double-edged modulation placement of the states is used, which requires recalculation of ta, tb, and to at the carrier crest, as well as at the trough. Over-modulation is when the magnitude of the demanded rotating vector is greater than /o pV such that the zero voltage time reduces to zero, to = 0, during a portion of the time of one rotation of the output vector. Initially this occurs at 30° ( )( )16 sector2 1Nπ − when the output vector length reaches / ,o pV as shown in figure 14.23b. As the demand voltage magnitude increases further, the region around the 30° vector position where to ceases to occur, increases as shown in figure 14.23c. When the output rotational vector magnitude increases to Vs, the maximum possible, angle α reduces to zero, and to ceases to occur at any rotational angle. The values of ta, tb, and to (if greater than zero), are calculated as usual, but pulse times are assigned pro rata to fit within the carrier period Tc. Power Inverters 456 (b) v1 v3 v7 v7 v3 v1 001 011 111 111 011 001 ½ ta ½ tb ¼ to ¼ to ½ tb ¼ ta Tc ΦR Φ Y ΦB v0 v1 v3 v7 v7 v3 v1 v0 000 001 011 111 111 011 001 000 ¼ to ½ ta ½ tb ¼ to ¼ to ½ tb ¼ ta ¼ to Tc (a) ΦR Φ Y ΦB ½v1 = ½Vs ½v3 = ½Vs v1 =Vs e j 0 001 VO/P θ / 2 sin 3b O P V V θ= V3 =Vs e j ? π 011 ( )13/2 sin3a O P V V π θ= − 000 111 SECTOR I 30° V3 =Vs e j ? π 011 v1 =Vs e j 0 001 000 111 SECTOR I Vs cos30° /o pV ∧ ta tb Tc Tc Tc (a) (b) /o pV V3 =Vs e j ? π 011 v1 =Vs e j 0 001 000 111 Tc Tc Tc tb + ta > Tc no to tb + ta < Tc reduced to tb + ta < Tc reduced to α 60°-α > // o po pV V (c) /o p jV e θ ωt Figure 14.23. First sector of inverter operational area involving pole outputs 001 and 011: (a) general rotating voltage vector; (b) maximum allowable voltage vector length for undistorted output voltages; and (c) over modulation. Figure 14.24. Assignment of pole periods ta and tb based on: (a) minimum current ripple and (b) minimum switching transitions per carrier cycle, Tc. docsity.com Power Electronics 461 Three types of resonant converters utilise zero voltage or zero current switching. load-resonant converters resonant-switch dc-to-dc converters resonant dc link and forced commutated converters The single-phase load-resonant converter, which is extensively used in induction heating applications, is presented and analysed in this chapter. Such resonant load converters use an L-C load which oscillates, thereby providing load zero current or voltage intervals at which the converter switches can be commutated with minimal electrical stress. Resonant switch dc-to-dc converters are presented in chapter 15.9. Two basic resonant-load single-phase inverters are used, depending on the L-C load arrangement: current source inverter with a parallel L-C resonant (tank) load circuit: switch turn-off at zero load voltage instants and turn-on with zero voltage switch overlap is essential (a continuous source current path is required) voltage source inverter with a series connected L-C resonant load: switch turn-off at zero load current instants and turn-on with zero current switch under lap is essential (to avoid dc voltage source short circuiting) Each load circuit type can be fed from a single leg (or arm) circuit or H-bridge circuit depending on the load Q factor. This classification is divided according to symmetrical full bridge for low Q load circuits (class D) single bridge leg circuit for a high Q load circuit (class E) High Q circuits can also use a full bridge inverter configuration, if desired, for higher through-put power. In induction heating applications, the resistive part of the resonant load, called the work-piece, is the active load to be heated - melted, where the heating load is usually transformer coupled. Energy transfer control complication is usually associated with the fact that the resistance of the load work-piece changes as it heats up and melts, since resistivity is temperature dependant. However, control is essentially independent of the voltage and current levels and is related to the resonant frequency which is L and C dependant. Inverter bridge operation is near the load resonant frequency so that the output waveform is essentially sinusoidal. By ensuring operation is below the resonant frequency, such that the load is capacitive, the resultant leading current can be used to self commutate thyristor converters which may be used in high power series resonant circuits. This same capacitive load commutation effect is obtained for parallel resonant circuits with thyristor current source inverters operating just above resonance. The output power is controlled by controlling the converter output frequency. 14.3.1 L-C resonant circuits L-C-R resonant circuits, whether parallel or series connected are characterised by the load impedance being capacitive at low frequency and inductive at high frequency for the series circuit, and visa versa for the parallel case. The transition frequency between being capacitive and inductive is the resonant frequency, ωo, at which frequency the L-C-R load circuit appears purely resistive and maximum power is transferred to the load, R. L-C-R circuits are classified according to circuit quality factor Q, resonant frequency, ωo, and bandwidth, BW, for both parallel and series circuits. The characteristics for the parallel and series resonant circuits are related since every practical series L-C-R circuit has a parallel equivalent, and vice versa. The parallel circuit can be series R-L in parallel with the capacitor C. As shown in figure 14.30 each resonant half cycle is characterised by the series resonant circuit current is zero at maximum capacitor stored energy the parallel resonant circuit voltage is zero at maximum inductor stored energy The capacitor in a series resonant circuit must have an external path through which to release its stored energy. The parallel resonant circuit can release its stored inductive energy within its parallel circuit, without an external circuit. The stored energy can internally resonate, transferring energy back and forth between the L and C, gradually dissipating in the circuit R, as heat. 14.3.1i - Series resonant L-C-R circuit The series L-C-R circuit current for a step input voltage Vs, with initial capacitor voltage vo and series inductor current io is given by ( ) ( )sin cost ts o oo V v i t e t i e t L α α ωω ω ω φωω − −−= × × + × × × + (14.75) where ( )2 2 2 2 2 1 11 tan 2 2 2 αω ω ξ ω α ω α ξ φ ωω = − = − = = = = =ando o o s o R R L Q LLC Power Inverters 462 i R jωL Vs v R jωL Is (a) (b) Z capacitive Z inductive |Z(ω)| R -90° +90° 1 θZ(ω) 0 ω=2πf Qs decreasing → √2 BWs ∞ ∞ ωℓ ωu Z capacitive Z inductive |Z(ω)| R -90° +90° 1 θZ(ω) 0 ω=2πf Qp decreasing → 1 √2 BWp 0 ωu ωℓ ωo ωo ωt high Q iseries low Q vcapacitor ideal commutation instants Vs ωt high Q vparallel low Q iinductor Is ideal commutation instants Is j Cω − j Cω − ξ is the damping factor. The capacitor voltage is important because it specifies the energy retained in the L-C-R circuit at the end of each half cycle. ( ) ( )( ) cos sint to oc s s o i v t V V v e t e t C α αωω ω φ ω ω ω − −= − − − + (14.76) At the series circuit resonance frequency ωo, the lowest possible circuit impedance results, Z = R, hence it can be termed, low-impedance resonance. The series circuit quality factor or figure of merit, Qs, is defined by 2 2 2 2 ½ 1 ½ / 2 π ωπ ξ × = = = = = = reactive power maximum stored energy average power energy dissipated per cycle o o o sQ L ZLi Ri f R R (14.77) Where the characteristic impedance is ( )o L Z C = Ω Figure 14.30. Resonant circuits, step response, and frequency characteristics: (a) series L-C-R circuit and (b) parallel L-C-R circuit. docsity.com Power Electronics 463 The series circuit half-power bandwidth BWs is given by 2o o s s s f BW Q Q ω π = = (14.78) and upper and lower half-power frequencies are related by ω ω ω= u . 4 ω ω α π = ± = ± o o u u Rf f L (14.79) Figure 14.30a shows the time-domain step-response of the series L-C-R circuit for a high Q load and a low Q case. In the low Q case, to maintain and transfer sufficient energy to the load R, the circuit requires re-enforcement every half sine cycle, while with a high circuit Q, re-enforcement is only necessary once per sinusoidal cycle. Thus for a high circuit Q, full bridge excitation is not necessary, yielding a simpler power circuit as shown in figure 14.31a and b. The energy transferred to the load resistance R, per half cycle 1/2fr, is ( ) 2 ½ 0 W i t R d t π ω ω= ∫ (14.80) The active power transferred to the load depends on the repetition rate of the excitation, fr. ½ (W)rP W f= × (14.81) Table 14.4 Characteristics and parameters of parallel and series resonant circuits characteristic series parallel Resonant period/time constant s LCτ = Resonant angular frequency rad/s 1 1 2o of LC ω π τ = = = Damping factor pu ½ ½s o o R C R L ξ ω ω = = 1 ½ ½op o L R C R ω ξ ω = = Damping constant /s 2s R L α = 1 2p CR α = Characteristic impedance Ω 1 o o o LZ L C C ω ω = = = Damped resonant angular frequency 2 2 21o oω ω ξ ω α= − = − rad/s 21o sω ω ξ= − 21o pω ω ξ= − Quality factor 1 s p Q Q = pu ( ) ( ) 2 2 1 2 2 ½1 ½ o o s s p o p LZ L Q C R RR LI CR RI ω ξ π ω τ = = = = = = ( )2 2 1 2 2 ½ ½ p o op p o p RRQ CR LZ C CVR L V R ω ξ π ω τ = = = = = =        Bandwidth rad/s os s BW Q ω = op p BW Q ω = 14.3.1ii - Parallel resonant L-C-R circuit The load for the parallel case is a parallel L-C circuit, where the active load is represented by series resistance in the inductive path. For analysis, the series L-R circuit is converted into its parallel R-L equivalent circuit, thus forming the equivalent parallel L-C-R circuit shown in figure 14.30b. A parallel resonant circuit is used in conjunction with a current source inverter, thus the parallel circuit is excited with a step input current. The voltage across a parallel L-C-R circuit for a step input current Is, with initial capacitor voltage vo and initial inductor current io is given by Power Inverters 464 ( ) ( ) ( )sin cost ts o oc co I i v t v t e t v e t C α α ωω ω ω ω φωω − −−= = × × + × × × + (14.82) The inductor current is important since it specifies the tank circuit stored energy at the end of each half cycle. ( ) ( ) ( )cos sint to oL s s o v i t I I i e t e t L α αωω ω φ ω ω ω − −= − − × × × − + × × (14.83) where 1 2CR α = The parallel circuit Q for a parallel resonant circuit is 1 p o o o s R R Q RC L Z Q ω ω = = = = (14.84) where Zo and ωo are defined as in equations (14.75) and (14.77), except L, C, and R refer to the parallel circuit values. The half-power bandwidth BWp is given by 2o o p p p f BW Q Q ω π = = (14.85) and upper and lower half power frequencies are related by uω ω ω= . At the parallel circuit resonance frequency ωo, the highest possible circuit impedance results, Z = R, hence it can be termed, high-impedance resonance. The energy transferred to the load resistance R, per half cycle 1/2fr, is ( ) 2 ½ 0 /W v t R d t π ω ω= ∫ (14.86) The active power to the load depends on the repetition rate of the excitation, fr. ½ (W)rP W f= × (14.87) Figure 14.31. Resonant converter circuits: (a) series L-C-R with a high Q; (b) low Q series L-C-R; (c) parallel L-C-R and high Q; and (d) low Q parallel L-C-R circuit. T1 D1 Vs T4 D4 C L R C R L T1 D1 T4 D4 T3 D3 T2 D2 T1 D1 T4 D4 T3 D3 T2 D2 L large I constant Vs C L R (a) (b) (c) (d) C L R Vs L large I constant T1 D1 T3 D3 VSI CSI docsity.com Power Electronics 465 IT1 t t t IT1 IT4 IT1 IT4 IT1 0 0 0 asymmetrical bridge conducting devices T1 D4 T4 D1 T1 D4 symmetrical H-bridge conducting devices T1 T2 D3 D4 T3 T4 D1 D2 T1 T2 D3 D4 φ lagging φ lagging Vref Vref Vref switch T4/T3 hard turn-off switch T1/T2 hard turn-off H-bridge output voltage Zero for half bridge 14.3.2 Series-resonant voltage-source inverters Series resonant circuits use a voltage source inverter (class D series) as considered in 14.1.1 and shown in figure 14.31a and b. If the load Q is high, then the resonance of energy from the energy source, Vs, need only be re-enforced every second half-cycle, thereby simplifying converter and control requirements. A high Q circuit is characterised by successive half-cycle capacitor voltage peak magnitudes being of similar magnitude, that is the decay rate is 1 2 1 1 π + = ≈ forn n c Q c v e Q v (14.88) Thus there is sufficient energy stored in C to be transferred to the load R, without need to involve the supply Vs. The circuit in figure 14.31a is simpler and control is easier. Also, for any Q, each converter can be used with or without the shown freewheel diodes. Without freewheel diodes, the switches have to block high reverse voltages due to the energy stored by the capacitor. MOSFET and IGBTs require series diodes to achieve the reverse voltage blocking requirements. In high power resonant applications, the reverse blocking abilities of the GTO and GCT make them ideal converter switches. Better load resonant control is obtained if freewheel diodes are not used. Figure 14.32. Series L-C-R high Q resonance using the converter circuit in figure 14.31a and b, with a lagging power factor φ. 14.3.2i – Series-resonant voltage-source inverter – single inverter leg Operation of the series load single leg circuit in figure 14.31a depends on the timing of the switches. Power Inverters 466 1 - Lagging operation (advancing the switch turn-off angle, f > fo) If the converter is operated at a frequency above resonance (effected by commutating the switches before the end of an oscillation cycle), the inductor reactance dominates and the load appears inductive. The load current lags the voltage as shown in figure 14.32. This figure shows the conducting devices and that a switch is turned on when its parallel connected diode is conducting. Turn-on therefore occurs at a low voltage (hence low switch turn-on loss and no need for fast recovery diodes), while turn-off is as with a hard switched inductive load (associated with switch high turn-off loss and turn-off Miller capacitance effects). Operation and switch timing are as follows: Switch T1 is turned on while its anti-parallel diode is conducting and the current in the diode reaches zero and the current transfers to, and begins to oscillate through the switch T1. The capacitor charges to a maximum voltage and before the current reverses, the switch T1 is hard turned off. The current is diverted through diode D4. T4 is turned on which allows the oscillation to reverse. Before the current in T4 reaches zero, it is turned off and current is diverted to diode D1, which returns energy to the supply. The resonant cycle is repeated when T1 is turned on before the current in diode D1 reaches zero and the process continues. 2 - Leading operation (delaying the switch turn-on angle, f < fo) By operating the converter at a frequency below resonance (effectively by delaying switch turn-on until after the end of an oscillation cycle), the capacitor reactance dominates and the load appears capacitive. The load current leads the voltage as shown in figure 14.33. This figure shows the conducting devices and that a switch is turned off when its parallel diode is conducting. Turn-off therefore occurs at a low current, while turn-on is as with a hard switched inductive load. Fast recovery diodes are therefore essential. Switch output capacitance charging and discharge (½CV2) and the Miller effect at turn-on (requiring increased gate power) are factors to be accounted for. Operation and switch timing are as follows: Diode D4 is conducting when switch T1 is turned on, which provides a step input voltage Vs to the series L-C-R load circuit, and the current continues to oscillate. The capacitor charges to a maximum voltage and the current reverses through D1, feeding energy back into the supply. T1 is then turned off with zero current. The switch T4 is turned on, commutating D1, and the current oscillates through the zero volt loop created through T4 and the load. The oscillation current reverses through diode D4, when T4 is turned off with zero current. T1 is turned on and the process continues. Without the freewheel diodes the half oscillation cycles are controlled completely by the switches. On the other hand, with freewheel diodes, the timing of switch turn-on and turn-off is determined by the load current zeros, if maximum energy transfer to the load is to be gained. Analysis – single inverter leg For a square wave input voltage, 0 to Vs, of frequency oω ω≈ , the input voltage fundament of magnitude 2 /πsV produces the dominant load current component, since higher frequency components are attenuated by second order L-C filtering action. That is, the resonant circuit excitation voltage is 2 si VV π= . The series circuit steady-state current at resonance for the single-leg half-bridge can be approximated by assuming ωo≈ω, such that in equation (14.75) io = 0: ( ) 1 sin 0 1 tsVi t e t t L e α απ ω ω ω ω π ω − −= × × × ≤ ≤ − (14.89) which is valid for the + Vs loop (through T1) and zero voltage loop (through T4) modes of cycle operation at resonance, provided the time reference is moved to the beginning of each half-cycle. In steady-state the successive capacitor voltage absolute maxima are / / / 1 1 1c cs s e V V V V e e απ ω απ ω απ ω −∧ ∨ − − = = − − − and (14.90) The peak-to-peak capacitor voltage is therefore ( ) / / 1 2coth / 2 1p pc s s s e V V V V e απ ω απ ω ωαπ ω απ− − − + = × = × ≈ × − (14.91) docsity.com Power Electronics 471 T1 D1 D4 T4 C 100µH 1Ω Vs 340V Ldc iC Idc Cdc 14.3.3ii – Parallel-resonant current-source inverter – H-bridge current-source inverter If the load Q is low, or maximum energy transfer to the load is required, the full bridge converter shown in figure 14.30d is used. Operation involves T1 and T2 directing the constant source current to the load and when the load voltage falls to zero, T3 and T4 are turned on (and T1 and T2 then turned off). Overlapping the switching sequence ensures a path always exists for the source current. At the next half sinusoidal cycle voltage zero, T1 and T2 are turned on and then T3 and T4 are turned off. The parallel circuit steady-state voltage for the symmetrical H-bridge can be approximated by assuming ωo ≈ ω, such that in equation (14.82) vo = 0: ( ) 2 sin 0 1 tsIv t e t t C e α απ ω ω ω ω π ω − −= × × × ≤ ≤ − (14.109) which is valid for both the + Is loops of cycle operation, provided the time reference is moved to the beginning of each half-cycle. In steady-state the successive inductor current absolute maxima are ( ) / / 1 coth / 2 1 LL s s e I I I I e απ ω απ ω απ ω −∧ ∨ − + = = × = − − (14.110) The energy transferred to the load R, per half sine cycle (per voltage pulse) is 2 / /2 0 0 2 2 sin / 1 2 coth 2 ts s IvW dt e t dtRR Ce LI π ω π ω α απ ω ω ω απ ω − −    = = × × ×  −   =     ∫ ∫ As with a series resonant circuit, the full bridge delivers four times more power to the load than the single-leg half-bridge circuit. Similarly, the load power and power factor can be controlled by operating above or below the resonant frequency, by delaying or advancing the appropriate switching instances. In the case of a voltage source, the expressions for the voltage across the load resistor are the same as equations (14.106) to (14.108), except the input voltage Vi is doubled, from 2Vs /π to 4Vs /π. Example 14.5: Single-leg half-bridge with a series L-C-R load An single-leg half-bridge inverter as shown in the figure 14.31a, with the dc rail L-C decoupling shown in figure 14.36, supplies a 1 ohm resistance load with series inductance 100 µH from a 340 V dc source. If the bridge is to operating at 10kHz, determine: i. the necessary series C for resonance at 10kHz and the resultant Q ii. the peak load current, its steady-state time domain solution, and peak capacitor voltages iii. the bridge rms voltage and fundamental voltage across the series L-C-R load iv. the power delivered to the load and the frequency when half power is delivered to the load. What is the switching advance/delay time? v. the peak blocking voltage of each semiconductor type (and for the case when the freewheel diodes are not employed) vi. the average, rms, and peak current in the switches and diodes vii. the resonant capacitor specification viii. the dc supply current and the dc link capacitor rms current ix. summarise conditions if the load is supplied from an H-bridge and also calculate the load power supplied at the third harmonic frequency, 3ω. Figure 14.36. Single-leg half-bridge series-resonance circuit. Power Inverters 472 Solution i. From 2 1/o of LCω π= = the necessary capacitance for resonance at 10kHz with 100µH is ( )2 1 2.5µF 2 10kHz 100µHπ = = × × × C The circuit quality factor Q is given by 100µH/ /1 6.3 2.5µF = = = Ω =o Z L Q R R C Therefore α = 5×103 Ω/H ω = 62.6 krad/s (9.968 kHz) Zo = 6.3 Ω ξ = 0.079 BWs = 9.97 krad/s (1.587kHz) ii. The steady-state current is given by equation (14.89) ( ) ( )5000 1 sin 1 245.5 sin 2 10kHz ts t V i t e t L e e t α απ ω ω ω ω π − − − = × × × − = × × × Since the Q is high (6.3), a reasonably accurate estimate of the peak current results if the current expression is evaluated at sin(½π), that is t =25µs, which yields i ∧ = 216.7A. The rms load current is 216.7A/√2 = 153.2A rms. From equation (14.90) the maximum capacitor voltage extremes are / / / 0.25 0.25 0.25 1 and 1 1 340V 340V 1 1 1537V 1197V c cs s e V V V V e e e e e απ ω απ ω απ ω −∧ ∨ − − − − − − = = − − = = − − − = = − iii. The bridge output voltage is a square wave of magnitude 340V and 0V, with a 50% duty cycle. The rms output voltage is therefore 340/√2=240.4V. Since the load is at resonance, the current is in phase with the fundamental of the bridge output voltage. The fundament voltage magnitude is given by 1 0 21 sin1 = 216.5V 2 = 153V π ω ππ π = = ≡ ∫ peak rms s s s V b V t V The rms load current results because of the fundamental voltage, that is, the peak sine current is 216.5V/1Ω = 216.5A peak or 153V/1Ω = 153A rms. This agrees with the current values calculated in part b. iv. The power delivered to the load is given by 2 2 1 2153A 1 23.41kW rms bP i R i R= = = × Ω = Substitution into equation (14.92) gives 23.15kW at a pulse rate of 2×10kHz. Alternately ×0.45 = 340V×0.45 153A=23.42kW = × = × × s s rmsP V I V I The half-power frequencies are when the reactive voltage magnitude equals the resistive voltage magnitude. 4 10kHz 796Hz u o R f f Lπ = ± = ± Thus at 9204 Hz and 10796 Hz the voltage across the resistive part of the load is reduced to 1/√2 of the inverter output voltage, since the voltage vectors are perpendicular. The power (proportional to voltage squared) is therefore halved (11.71kW) at the half-power frequencies. Operating above resonance, f > fo produces an inductive load and this is achieved by turning T1 and T4 off prematurely. Zero current turn-on occurs, but hard switching results at turn-off. To operate at the docsity.com Power Electronics 473 10796Hz (92.6µs) upper half-power frequency the period has to be reduced from 100µs (10kHz) to 92.6µs. The period of each half cycle has to be reduced by ½×(100µs - 92.6µs) = 3.7µs Operating below resonance, f < fo produces a capacitive load and this is achieved by turning T1 and T4 on late. Zero current turn-off occurs, but hard switching results at turn-on. By delaying turn-on of each switch by ½×(109µs - 100µs), 4.5µs, the effective oscillation frequency will be decreased to the lower half-power frequency, 9204Hz. v. The bridge diodes, which do not conduct at resonance, clamp switch and diode maximum supporting voltages to the rail voltage, 340V dc. Note that if clamping diodes were not employed the device maximum off-state voltages would occur during switch change over, when one switch has just been turned off, and just before the on-going switch is turned on. The load current is zero, so the load terminal voltage is the capacitor voltage. Switch T1 would need to support a forward voltage of Vs - v ∨ = 340V + 1197V =1537V = v ∧ and a reverse voltage of v ∧ - Vs = 1537V - 340V = 1197V = - v ∨ , while Switch T4 supports a forward voltage of v ∧ = 1537V and a reverse voltage of - v ∨ = 1197V. Thyristor family devices must be used, or devices with a series connected diode, which will increase the converter on-state losses. vi. At resonance the two freewheel diodes do not conduct. The rms load current is 153.2 A at 10 kHz, where switch T1 conducts half the cycle and T4 conducts the other half which is the opposite polarity of the cycle. Each switch therefore has an rms current rating of 153.2/√2 = 108.3A rms. Since both switches conduct the same current shape, each has an average current rating of a half-wave rectified sine of magnitude 216.5A, that is 1 0 1 1216.5sin 216.5A 2 0.45 216.5 / 2 68.9A π ω π π = = × = × = ∫TI t dt By Kirchhoff’s current law, this current value for T1 is also equal to the average dc input current from the supply Vs. vii. The 2.5µF capacitor has a bipolar voltage and current requirement of ±1537V and ±216.7 A. The rms ratings are therefore ≈1087V rms and 153A rms. A metallised polypropylene capacitor capable of 10kHz ac operation, with a maximum dv/dt rating of approximately ½×(1537+1197)×ω, that is 85.6V/µs, is required. viii. The dc supply current is the average value of the half-wave rectified sinusoidal load current, which is the average current in T1. That is 0.45 153.1A rms = 68.9A dc dcI = × The rms current in the dc link capacitor Cdc is related to the dc input current and switch T1 rms current (as found in part vi.), by 2 2 2 2108.3 68.9 83.6A rms = − = − = c rms dcI I I ix. The load dependant parameters C, ωo, ω, α, Q, BW, ξ, and half power points remain unchanged, being independent of switching frequency. From equation (14.96) the steady-state current is double that for the asymmetrical bridge, ( ) ( )5000 2 sin 1 491 sin 2 10kHz ts t V i t e t L e e t α απ ω ω ω ω π − − − = × × × − = × × × The peak current is i ∧ = 433.4A. The rms load current is 433.4A/√2 = 306.4A rms From equation (14.97) both the maximum capacitor voltages are Power Inverters 474 / / 0.25 0.25 1 1 1340V 2734V 1 c cs e V V V e e e απ ω απ ω −∧ ∨ − − − + = = − − + = = − The power delivered to the load is four times the single-leg half-bridge case and is 2 2306.4A 1 93.88kWrmsP i R= = × Ω = The average switch current is 194.8A, but the average supply current is four times the single-leg half- bridge case and is 275.5.6A. For a square wave, the third harmonic is a third the magnitude of the fundamental. From equation (14.101), for operation at the lower half power frequency 9204Hz, (which would result in the largest harmonic component magnitude after L-C filtering attenuation) f3 = 27.6kHz. ( )½ 2 2 ½ ½ 2 2 2 2 1 3 1 3 1 3 4 1 31 3 4 340V 1 3 2 9.204 Hz 2 10kHz1 6.3 2 10kHz 3 2 9.204 Hz 4 340V 1 3 9.204 101 6.3 10 3 9.204 144.3V 0.066 = 9.53V s R o o V v Q k k ω π ω ω ω ω π π π π π π − − − = ×   + −    × = × × + − ×  × = × × + − ×  = × × × × The magnitude of the third harmonic current is therefore 9.5V/1Ω = 9.5A or 6.7A rms. The load power at this frequency is 6.7V2/1Ω = 45.1W. This is clearly insignificant compared to the fundament power of 93.88kW being delivered to the 1 Ω load. ♣ 14.3.4 Single-switch, current source, series resonant inverter The single switch inverter in figure 14.35 is applicable to high Q load circuits such that the output is essentially sinusoidal, with zero average current. Based on the operating mechanisms, a sinusoidal current implies the switch has a 50% duty cycle. The switch turns on and off at zero volts so switch losses are low, so the operating frequency can be high. The input inductor Llarge in conjunction with the input voltage source, during steady state operation, act as a current source input, Is, for the resonant circuit, such that Vs Is is equal to the power delivered to the load R. When the switch T1 is turned on, with zero terminal voltage, it conducts both the constant current Is and the current io resonating in the output circuit, as shown in the circuit waveforms in figure 14.35. The resonating load current builds up. The switch T1, which is in parallel with Cs, is turned off. Current from the switch is diverted to Cs, which charges from an initial voltage of zero. Cs thus forms a turn-off snubber in parallel with T1. The charge on Cs eventually resonates back to zero at which instant the switch is turned on, again, with zero turn-on loss. The resonant frequency is 1/o o oL Cω = and because of the high Q, a small change in the switching frequency significantly decreases the output current, hence output voltage. As with any current source inverter, the peak switch voltage is in excess of Vs. Since the current is sinusoidal, the average load voltage and inductor voltage are zero. Therefore the average voltage across Co and Cs is the supply voltage Vs. The peak switch voltage can be estimated to be in excess of Vs /0.45 which is based on a half-wave rectified average sinusoidal voltage. If the load conditions change and the switch duty cycle is varied from δ = ½, circuit voltages increase and capacitor Cs voltage discharges before the circuit current reaches zero. The capacitor and switch are bypassed with current flowing through the diode D1. This diode prevents the switch from experiencing a negative voltage and the capacitor from charging negatively. Although such resonant converters offer features such as low switching losses and low radiated EMI, optimal control and performance are difficult to maintain and extremely high circuit voltages occur at low duty cycles. docsity.com Power Electronics 475 Figure 14.35. Single-switch, current-source series resonant converter circuit and waveforms. 14.4 Multi-level voltage-source inverters The conventional three-phase, six-switch dc to ac voltage-source inverter is shown in figure 14.7. Each of the three inverter legs has an output which can provide one of two voltage levels, Vs, when the upper switch (or diode) is on, and 0 when the lower switch (or diode) conducts. The quality of the output waveform is determined by the resolution and switching frequency of the pwm technique used. A multilevel inverter (directly or indirectly) divides the dc rail, so that the output of the leg can be more than two discrete levels, as shown in figure 14.37 for a diode clamped multilevel inverter model. In this way, the output quality is improved because both pulse width modulation and amplitude modulation can be used. The output pole is made from more than two series connected, clamped switches, so the total dc voltage rail can be the sum of the voltage rating of the individual switches. Very high output voltages can be achieved, where each device does not experience a voltage in excess of its individual rating. Rload Vs Lo Co io T1 D1 Cs Is iT iD1 iCs Llarge 1/2fo switch conducting switch off switch conducting io Is iT1 iCs VT1 Is Is iD1 1/2fo δ=½ IT1 = Is + io iCs = Is + io IT1 Rload ↑ Is io ICs Rload ↑ Is io Power Inverters 476 Figure 14.37. One phase leg of a voltage-source bridge inverter with: (a) two levels; (b) three levels; and (c) N-levels, with N-1 capacitors and waveform for five levels. A multilevel inverter allows higher output voltages with low distortion (due to the use of both pulse width and amplitude modulation) and reduced output dv/dt. There are three main types of multilevel converters • Diode clamped • Flying capacitor, and • Cascaded H-bridge 14.4.1 Diode clamped multilevel inverter Figure 14.37 shows the basic principle of the diode clamped (or neutral point clamped, NPC) multilevel inverter, where only one dc supply, Vs, is used and N is the number levels present in the output voltage between the leg output and the inverter negative terminal, Va-neg. The capacitors split the dc rail voltage into a number of lower voltage levels, each of which can be tapped and connected to the leg output through switches (and diodes). Only one string of series connected capacitors is necessary for any number of output phase legs. The number of levels in the line-to-line voltage waveform will be 2 1k N= − (14.111) while the number of levels in the line to load neutral of a star (wye) load will be 2 1p k= − (14.112) The number of capacitors required, independent of the number of phase, is 1capN N= − (14.113) while the number of clamping diodes per phase is ( )2 1clampD N= − (14.114) The number of possible switch states is phasesstatesn N= (14.115) and the number of switches in each leg is ( )2 1nS N= − (14.116) The basic three-level inverter (±½Vs, 0) is shown in figure 14.38, along with the basic three-level voltage from the leg output to centre tap of the capacitor string, R (neutral point). When switch T1 is on, its complement T1′ is off, and visa versa. Similarly for the pair of switches T2 and T2′. Specifically T1 and T2 on give the output +½Vs, T1′ and T2′ on give the output -½Vs, and T2 and T1′ on give the output 0. Essential to attaining these output levels, are the clamping diodes Du and Dℓ. These two diodes clamp the outer switches to the capacitor string mid-point, which is half the dc rail voltage. In this way, no switch experiences a voltage in excess of half the dc rail voltage. Inner switches must be turned on (or off) before outer switches are turned on (or off). (a) (b) (c) 0 0 0 a a a Va0 Va0 Va0 ½Vs Vs /N-1 ½Vs Vs /N-1 Vs /N-1 Vs Vs Vs Vs +½Vs -½Vs +½Vs -½Vs +¼Vs +½Vs -¼Vs -½Vs 0V 0V t t t docsity.com Power Electronics 481 T1 D1 T3 D3 D2 T2 D4 T4 V1 Vs T1 D1 T3 D3 D2 T2 D4 T4 V1 Vs T1 D1 T3 D3 D2 T2 D4 T4 V1 Vs Figure 14.41. One leg of a voltage-source, seven-level, cascaded H-bridge inverter. A comparison between the three basic multilevel inverters is possible from the numerical summary of component numbers for each inverter, as in Table 14.8. The diode clamped inverter requires many clamping diodes; the flying capacitor inverter requires many independent capacitors; while the cascaded inverter requires many isolated dc voltage power supplies. Table 14.8. Multilevel inverter component count, per phase. * either /or 14.4.4 PWM for multilevel inverters Two basic approaches can be used to generate the necessary pwm signals for multilevel inverters. Each approach is based on the extension of a two level equivalent. • Modulating waveform comparison with offset triangular carriers • Space vector modulation based on a rotating vector in multilevel space levels Inverter type VA-0V VA-B VA-N switches & // diodes diodes clamping flying capacitors Level capacitors Isolated supplies diode clamped N 2N-1 4N-3 2(N-1) (N-1)(N-2) 0 (N-1) 0 fly capacitor N 2N-1 4N-3 2(N-1) 0 ½(N-1)(N-2) (N-1) 0 cascade N 2N-1 4N-3 2(N-1) 0 0 ½ (N-1)* ½(N-1)* Power Inverters 482 Figure 14.42. Multi-carrier based pwm generation for 1 phase of a voltage-source, 5-level, inverter. 14.4.4i - Multiple offset triangular carriers Various sinusoidal pwm techniques were considered in sections 14.1.3v and 14.1.3vi of this chapter. Figure 14.42 shows how a triangular carrier is associate with each complementary switch pair, four carriers (N-1) for the five-level inverter as illustrated. The parts of figure 14.42 show how the four individual carriers can be displaced with respect to one another. The figure also shows how triplen injection is incorporated. The appropriate five-level switch states, as in tables 14.4 to 14.6, can be used to decode the necessary switching sequences. To minimise losses, switching only occurs between adjacent levels. 14.4.4ii - Multilevel rotating voltage space vector Space vector modulation for the two-level inverter was considered in section 14.1.3vi of this chapter. The basic hexagon shape for two levels is extended to higher levels as shown in figure 14.43, for three levels. The number of triangles, vectors, and states increases rapidly as the level number increases. Table 14.9. Properties of N-level vector spaces levels states triangles vectors N N3 6(N-1)2 3N(N-1)+1 vectors in each hexagon 2 8 6 7 (1+6) 3 27 24 19 (1+6)+12 5 125 96 61 (1+6)+12+18+24 1 ½ 0 -½ -1 ½Vs ¼Vs 0 -¼Vs -½Vs 0 0 π π 0 0 0 0 docsity.com Power Electronics 483 From table 14.9, the states for the two and three level inverters can be specified as follows. The 2-level inverter The zero state matrix is [ ]000 111 The first and only hexagon is shown in figure 14.22a. [ ]100 110 010 011 001 101 The three level inverter The zero state matrix is [ ]000 111 222 The first hexagon matrix is 100 110 010 011 001 101 211 221 121 122 112 212       The second hexagon matrix is [ ]200 210 220 120 020 021 022 012 002 102 202 201 These pole states are shown figure 14.43. Figure 14.43. Rotating voltage space vector approached applied to three phases of a voltage-source three-level, inverter. A 0  represents the minimum voltage obtainable from the multilevel converter and N-1 represents the maximum value. For example, in a two-level converter, 0  is equivalent to 0V and 1  is equivalent to Vs, where Vs is the converter DC link voltage. In a three-level converter 0  is equivalent to -½Vs, 1  is equivalent to 0 V, and  ‘2’ is equivalent to ½Vs where Vs is the dc link voltage of the multilevel converter. When the rotating vector is drawn in the vector space, it is decomposed into vectors bordering the triangle it lies in. When operating in the outer hexagon, the vectors states used in the inner most hexagon mean that that level of the converter is operating with a six-step quasi-square output voltage waveform, to which is added a modulated square waveform for the next higher level. 14.5 Reversible dc link converters Power inversion by phase angle control is attained with a fully controlled single-phase converter as discussed in section 11.3.3. Power regeneration is also possible with the fully controlled three-phase converter shown in figure 11.17. If a fully controlled converter supplies a dc machine, two-quadrant control is possible (QI and QIV), motoring in one direction of rotation and generating in the other direction. Power regeneration into the supply is achieved by reversing the dc output voltage by controlling the converter phase delay angle. The converter current is uni-directional, that is, the converter output current can not reverse. The dual or double converter circuit in figure 14.44a and b will accommodate four-quadrant dc machine operation, where the circuit performs as two fully controlled converters in anti-parallel. Each converter is able to rectify and invert, but because of their inverse parallel connection, one converter (the positive converter P) operates in quadrants QI and QIV, while the other (the negative converter N) operates in quadrants QII and QIII, as shown in figure 14.45. The two converters can be operated synchronously, called simultaneous control or independently where one is always blocking, called independent control. 020 000 210 120 021 110 001 011 202 200 201 111 222 122 010 121 101 221 100 211 212 112 022 002 102 220 012 Power Inverters 484 Figure 14.44. Reversible converter allowing four-quadrant control of: (a) a dc machine with independent converters; (b) a dc machine with simultaneously controlled converters; and (c) voltage and (d) current fed induction machine. 14.5.1 Independent control Simultaneous converter control can be used if continuous load current can be guaranteed. Otherwise only one converter, depending on the quadrant, need operate at anyone time (the other is in a blocking state), as shown in figure 14.44a. No circulating currents arise due to possible mismatched N and P converter output voltages. The continuous current condition may be difficult to ensure at light load levels. Additional series armature inductance, L in figure 14.44a and b, helps with current smoothing and ensuring continuous machine current. dc link (a) (b) (c) α1 α1 α1 α2 α2 α2 rectifier/ converter inverter dc link input L-C filter output filter 3Φ input 3Φ output ½ L (d) P N L L P N P N docsity.com Power Electronics 485 A machine rotational direction change is affected by the following converter operating procedure. • Initially the motor is operating in quadrant I, with 0° ≤ α1 ≤ 90° for the positive converter P. The negative converter, N, is in the fully blocking state, with all thyristors turned off. • The positive converter is put into the inverting mode with 90° ≤ α1 ≤ 180°, changing the average output voltage from positive to negative. The machine current rapidly falls to zero. The machine rotational speed slows, the rate depending on the load inertia. • After a dead time, the positive converter blocks and the negative converter N starts in a motor braking mode in quadrant II. The motor speed falls rapidly to zero. • The second converter operates in quadrant III and rapidly accelerates the motor in the opposite direction, with 0° ≤ α2 ≤ 90°. The dead time before turning on the negative converter N is to ensure the positive converter P is fully off, otherwise the three-phase input voltage lines may short through the two converters. Such a current condition cannot be controlled with line-commutated thyristors. Operation is characterised by transitions from QI to QII to QIII for reversal, and transitions from QIII to QIV to QI for returning to the original direction of rotation. Figure 14.45. Four quadrants of reversible converter operation. 14.5.2 Simultaneous control Simultaneous converter control, also called circulating current control, functions with both converters always in operation which gives a faster dynamic response than when the converters are used mutually exclusively. To avoid supply short circuits requires that the output voltage of both converters (rectifier Vr and inverter Vi) be the same in order to minimise circulating currents. 1 2 1 2 1 2 0 cos cos 0 cos cos 0 180 α α α α α α + = + = + = + = °that is r iV V V V (14.129) Equation (14.129) implies that both converters operate with firing angles that sum to 180°. Each converter produces the opposite polarity output voltage, which is cancelled by reversing the relative output connections. Under such conditions the load current can be maintained continuous. To minimize any circulating current due to ripple voltage produced by instantaneous voltage differences between the two converters, inductance is usually inserted between each converter and the dc machine load, as shown in figure 14.44b. Adversely the cost and weight are increased, and the supply power factor and drive efficiency are decreased, compared to that obtained with independently controlled converters. + E Ia E + Ia + E Ia E + Ia torque Ia speed vo II I III IV m otor/rectification regenerative braking /inversion regenerative braking /inversion m otor/rectification α1 α1 α2 α2 N N P P vo vo vo vo Power Inverters 486 A machine rotational direction change is affected by the following converter operating procedure. • Initially the motor is operating in quadrant I for the rectifying, positive converter, with 0° ≤ α1 ≤ 90°. The other converter is operating in the inverting mode with 90° ≤ α2 ≤ 180°, such that α1 + α2 = 180°. The output voltage for both converters is the same, and the negative converter N carries only the circulating current. • For rotational direction reversal, α1 ≥ 90° and α2 ≤ 90°, such that α1 + α2 = 180°. The armature back emf voltage now exceeds the converter output voltages, and current diverts to the negative converter N and the machine regeneratively brakes, operating in quadrant II. The current rapidly falls to zero and the positive converter P carries only the ac circulating current. • The speed rapidly falls to zero, with α1 = α2 = 90° giving zero output voltage, so as to control the armature current since the back emf is zero. Then with α2 < 90° the machine rapidly accelerates in quadrant III, in the reverse direction to the original rotation. For reversing the direction of rotation from Q III the operation sequence is QIII to QIV to QI. Since no converter dead time is introduced, a fast dynamic response can be attained. A small dc circulating current is deliberately maintained, that is greater in magnitude than the peak of the ac ripple current. The ac current can then flow continuously in both converters, both of which can operate in the continuous conduction mode without the need for continuous converter current reversal operation. 14.5.3 Inverter regeneration The bridge freewheel diodes of a three-phase inverter restrict the dc rail or dc link voltage from reversing. The dual or double converter circuit in figure 14.44c will allow inversion with a three-phase voltage source inverter. One converter rectifies, the other converter inverts, functioning as a self- commutated inverter, transferring power from the dc link to the ac supply. Complete four-quadrant control of the three-phase ac machine on the inverter is achieved in conjunction with control of the dc to ac inverter. That is, motor reversal is achieved by effectively interchanging the pwm control signals associated with two phases. The real power flow back into the ac supply is controlled by the converter phase delay angle, while the reactive power flow is controlled by the voltage magnitude. The angle and voltage are not independent. In the case of a pwm controlled inverter fed ac machine, the ac to dc converter can be uncontrolled, using all diodes, since dc output voltage reversal is not utilised. Figure 14.44d shows a fully reversible current controlled converter/inverter configuration, using self- commutating devices. The use of self-commutated switches (rather than mains commutated converter thyristors) offers the possibility to minimise the input current distortion and to reduce the inductor size hence improve the dynamic current response. The switch series diodes are essential since the shown IGBTs have no useable reverse blocking capability. The use of reverse blocking GCTs avoids the need for the series blocking diodes, which reduces the on-state voltage losses but increases gate drive complexity and power rating. Series connection of devices is necessary above a few kV, and above 1 MVA the GCT dominates. 14.6 Standby inverters and uninterruptible power supplies Standby inverters and uninterruptible power supplies (ups’s) provide a 50/60 Hz supply in the event of an ac mains failure. An ups must provide ac output such that mains failure is undetected by the load. To achieve this, an ups continually feeds the load from an inverter. A load that can tolerate a short interruption of the ac supply is fed from a standby inverter which becomes operational within 1-5 ms after the ac supply failure. In communications, computing, and automated production lines, ups’s are essential for even brownouts (V and f outwith bounds for reliable equipment operation), while in lighting and heating applications, standby inverters are used since a few missing ac cycles (due to a blackout – total interruption of the mains power) may be tolerated. In each power supply case, the alternative energy source is a standby dc battery. The ups keeps the battery charged when the ac input is supplying the output power. 14.6.1 Single-phase UPS A basic single-phase UPS is shown in figure 14.46. A key safety objective is to retain the supply neutral at both the supply input and the ac output, without resorting to any from of isolating transformer. Consequently, the input ac mains is half-wave rectified by diodes and R RD D+ − . Boost converters on the positive and negative groups ensure supply sinusoidal input current and unity power factor. The output H-bridge (T1-T4) uses pwm and feedback control to produce a fixed frequency and magnitude output docsity.com