Sample Exam for CSC 501, Exams of Operating Systems

Download Sample Exam for CSC 501 and more Exams Operating Systems in PDF only on Docsity! Name: __________________ Unity ID: __________________ Student ID: __________________ 1 CSC-501: Operating Systems Principles (Fall 2015) I’m in Monterey; You’re Taking an Exam Please Read All Questions Carefully! There are ten (10) total numbered pages. Please put your Name, Unity ID, and student ID on THIS page, and JUST YOUR student ID (but NOT YOUR NAME or UNITY ID) on every other page. Why are you doing this? So I can grade the exam anonymously. So, particularly important if you think I have something against you! But of course, I don’t. Probably. The exam is closed everything (books, notes, discussion, cell phone, and computer), but you can have one double- sided letter-size cheat-sheet. You have 75 minutes. Your work must be individual. Cheating will be punished instantly. Please focus on your own exam. Name: ______________________ Unity ID: ______________________ Student ID: ______________________ Name: __________________ Unity ID: __________________ Student ID: __________________ 2 Grading Page Points Total Possible Q1 10 Q2 10 Q3 15 Q4 15 Q5 15 Q6 15 Q7 10 (bonus 10) Total 100 (bonus 10) Name: __________________ Unity ID: __________________ Student ID: __________________ 5 2. Subtle Differences: In this question, we’ll examine some subtle differences within an OS; your job is to determine what the effects of these small changes are on the behavior of the operating system (a) With the round robin (RR) scheduling policy, a question arises when a new job arrives in the system: should we put the job at the front of the RR queue, or the back? Does this subtle difference make a difference, or does RR behave pretty much the same way either way? (Explain) (b) The multi-level feedback queue policy periodically moves all jobs back to the top-most queue. On a particular system, this is usually done every 10 seconds; the subtle difference we examine is that this value has been shortened to 1 second. How does this subtle difference affect the MLFQ scheduler? In general, what is the effect of shortening this value? (c) The timer interrupt is a key mechanism used by the OS. Usually, it waits some amount of time (say 10 milliseconds) and then interrupts the CPU. In this subtle difference, the interrupt is not based on time but rather based on the number of TLB misses the CPU encounters; once a certain number of TLB misses take place, the CPU is interrupted and the OS runs. How does this subtle difference affect the timer interrupt and its usefulness? Name: __________________ Unity ID: __________________ Student ID: __________________ 6 3. Paging and Page Tables. Assume the following: a 32-bit virtual address space, with a 1KB page size. (a) How many bits are in the offset portion of the virtual address? (b) How many bits are in the VPN portion of the virtual address? Now, let’s focus on the page table. Assume each page table entry is 4 bytes in size. Assuming a linear page table: (c) How many entries are in the table? (d) What is the total size of the table? (e) In a live system, how much memory would be occupied by page tables? (What factors affect this?) Linear page tables are too big. Hence, people came upon the idea of a multi-level page table, which uses a page directory to point to page-sized chunks of the page table. Assume we wish to build such a table, with two levels (as discussed in class). To access such a table, the VPN is split into two components: the VPNPageDir which indexes into the page directory, and the VPNChunkIndex which indexes into the page of the page table where the PTEs are located. (f) How many PTEs fit onto a single page in this system? (g) How many bits are thus needed in the VPNChunkIndex? (h) How many bits are needed in the VPNPageDir? (i) How much memory is needed for the page directory? Finally, given the following memory allocations, write down both (a) how much memory our multi-level page table consumes and (b) how much memory a linear page table consumes: (j) Code is located at address 0 and there are 100 4-byte instructions. The heap starts at page 1 and uses 3 total pages. The stack starts at the other end of the address space, grows backward, and uses 3 total pages. • Multi-level page table size? • Linear page table size? (k) Code is located at address 0 and there are 100 4-byte instructions. The heap starts at page 1 and uses 1000 total pages. The stack starts at the other end, grows backwards, and uses 1000 total pages. • Multi-level page table size? • Linear page table size? (l) The entire address space (every page) is used by the process. • Multi-level page table size? • Linear page table size? Name: __________________ Unity ID: __________________ Student ID: __________________ 7 4. Tracing Virtual Memory. This question asks you to consider everything that happens in a system on a memory reference. Assume the following: 32-bit virtual addresses, 4KB page size, a 32-entry TLB, linear page tables (if it matters), and LRU replacement policies whenever such a policy might be needed by either hardware or software. Assume further that there are only 1024 pages of physical memory available. In this question, you will be running some test code and saying what happens when that code is run. Before the test code is run, though, the following initialization code is run once (before testing begins). This code simply allocates (NUM PAGES*PAGE SIZE) number of bytes and then sets the first integer on each page to 0, where PAGE SIZE is 4KB (as above) and NUM PAGES is a constant (defined below). Assume malloc()returns page-aligned data in this example. // allocate NUM_PAGES*PAGE_SIZE bytes void *orig = malloc(NUM_PAGES * PAGE_SIZE); void *ptr = (int *) orig; for (i = 0; i < NUM_PAGES; i++) { *ptr = 0; // init first value on each page ptr += PAGE_SIZE; } The code we are now interested in running, which we will call the test code, is the following: ptr =(int *) orig; for (i = 0; i < NUM_PAGES; i++) { int x = *ptr; // load value pointed to by ptr ptr += PAGE_SIZE; } For these questions, assume we are only interested in memory references to the malloc’d region through ptr (that is, ignore stores to x and instruction fetches). How many TLB hits, TLB misses, and page faults occur during the test code when ... TLB hits TLB misses Page Faults (a) NUM PAGES is 16? (b) NUM PAGES is 32? (c) NUM PAGES is 2048? Assume a memory reference takes roughly time M and that a disk access takes time D. How long does the test code take to run (approximately), in terms of M and D, when... TLB hits TLB misses Page Faults (d) NUM PAGES is 16? (e) NUM PAGES is 32? (f) NUM PAGES is 2048? Now assume we change the various replacement policies in the system to MRU. Given this change, how long does the test code take to run (approximately), in terms of M and D, when... TLB hits TLB misses Page Faults (g) NUM PAGES is 16? (h) NUM PAGES is 32? (i) NUM PAGES is 2048? Finally, assume you are to run this code on a new machine that you know very little about. In fact, you wish to use the test code to learn how big the TLB is and how much memory is on the given system. (j) How could you use the test code above to learn these facts about the physical hardware?