# Shift Register - Design Techniques for Digital Systems - Lecture Slides, Slides for Digital Systems Design. Biju Patnaik University of Technology, Rourkela

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In the course of the Design Techniques for Digital Systems, we study the key concept regarding the digital system. The major points in these lecture slides are:Shift Register, Standard Sequential Modules, Register and Co...
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CS 140 Lecture 6

1

Standard Sequential Modules

1. Register

2. Shift Register

3. Counter

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2

Counter

• Applications?

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Counter: Applications

• Program Counter

• Clock Divider

• Sequential Machine

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Counter

• Modulo-n Counter

• Modulo Counter (m<n)

• Counter (a-to-b)

• Counter of an Arbitrary Sequence

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Modulo-n Counter

LD

D

Q

TC

Q (t+1) = (0, 0, .. , 0) if CLR = 1

= D if LD = 1 and CLR = 0

= (Q(t)+1)mod n if LD = 0, CNT = 1 and CLR = 0

= Q (t) if LD = 0, CNT = 0 and CLR = 0

CNT

CLR Clk

TC = 1 if Q (t) = n-1 and CNT = 1

= 0 otherwise

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Modulo-m Counter (m< n) Given a mod 16 counter, construct

a mod-m counter (0 < m < 16) with AND, OR, NOT gates

m = 6 Q3 Q2 Q1 Q0

3 2 1 0

CLK

CLR

CNT

D3 D2 D1 D0

0 0 0 0

LD

Q2 Q0

X

Set LD = 1 when X = 1 and (Q3Q2Q1Q0) = (0101), ie m-1

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A 5-to-11 Counter

Q3 Q2 Q1 Q0

Clk

CLR

CNT

D3 D2 D1 D0

0 1 0 1 (a)

LD

Q3

Q0

X

Set LD = 1 when X = 1 and (Q3Q2Q1Q0) = b (in this case, 1011)

Counter (a-to-b) Given a mod 16 counter, construct an a-to-b counter

(0 < a < b < 15)

Q1 (b)

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Given a mod 16 counter, construct

a counter with sequence 0 1 5 6 2 3 7

Q2 Q1 Q0

Clk

CLR

CNT

D2 D1 D0 LD

Q2’ Q0

X

Q2 Q0 Q1 Q0 Q0’

When Q = 1, load D = 5

When Q = 6, load D = 2

When Q = 3, load D = 7

Counter of an Arbitrary Sequence

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LD = Q2’ Q0 + Q2Q0’

D2 = Q0

D1 = Q1

D0 = Q0

K Mapping LD and D,

we get Id Q2Q1Q

0 LD D2 D1 D0

0 000 0 - - -

1 001 1 1 0 1

2 010 0 - - -

3 011 1 1 1 1

4 100 - - - -

5 101 0 - - -

6 110 1 0 1 0

7 100 0 - - -

Given a mod 16 counter, construct

a counter with sequence 0 1 5 6 2 3 7

Counter of an Arbitrary Sequence

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D2 = Q0

D1 = Q1’ + Q0

D0 = Q1’Q0

LD = Q2’ Q1’ + Q2Q0 + Q2 Q1

Through K-map, we derive

Count in sequence 0 2 3 4 5 7 6

LD = 1 D = 2 When Q(t) = 0

LD = 1 D = 7 When Q(t) = 5

LD = 1 D = 6 When Q(t) = 7

LD = 1 D = 0 When Q(t) = 6

Id Q2Q1Q0 LD D2 D1 D0

0 000 1 0 1 0

1 001 - - - -

2 010 0 - - -

3 011 0 - - -

4 100 0 - - -

5 101 1 1 1 1

6 110 1 0 0 0

7 100 1 1 1 0

Counter of an Arbitrary Sequence

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CNT

LD

TC

Clk

Q7,Q6,Q5,Q4

D7,D6,D5,D4

CNT

LD

TC

Clk

Q3,Q2,Q1,Q0

D3,D2,D1,D0

X TC0

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TC = 1 when (Q3,Q2,Q1,Q0 )=(1,1,1,1) and X=1 (Q7 (t+1) Q6 (t+1) Q5 (t+1) Q4 (t+1) ) = (Q7 (t) Q6 (t) Q5 (t) Q4 (t) ) + 1 mod 16

when TC0 = 1

The circuit functions as a modulo 256 counter.

Time 0 1 2 3 … 13 14 15 16 17 18 19

Q7-4 0 0 0 0 … 0 0 0 1 1 1 1

TC0 0 0 0 0 … 0 0 1 0 0 0 0

Q3-0 0 1 2 3 … 13 14 15 0 1 2 3

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