# Test Paper - Digital Logic Design and Application - Computer Engineering - 3rd Semester

SRflip-flop ,  D flip-flop, K Map, multiplexer and OR gates, Gray code, TTL and CMOS logic families, Code converters, Error detecting and correcting code, ALU, Priority Encoder, one bit BCD adder, Quine McCluskey tabular method.

# Synchronous Sequential Circuits-Digital Logic-Lecture 27 Slides-Electrical and Computer Engineering

Synchronous Sequential Circuits, State Diagrams, State Tables, Moore Model, Mealy Model, Finite State Machines, FSM, Active Clock Edge, Reset, Present State, Next State, State Variables, Digital Logic, Lecture Slides, Dr D J Jackson, Department of...

# Logic Circuits-Digital Logic-Lecture 02 Slides-Electrical and Computer Engineering

Logic Circuits, Variables, Functions, Truth Tables, Gates, Networks, Binary, Boolean, Algebra, AND, OR, Inversion, Analysis, Logic Network, Digital Logic, Lecture Slides, Dr D J Jackson, Department of Electrical and Computer Engineering, Universit...

# Combinatorial Circuit Building Blocks-Digital Logic-Lecture 22 Slides-Electrical and Computer Engineering

Combinatorial Circuit Building Blocks, Multiplexers, Decoders, Demultiplexers, Encoders, Code, Converters, 2 to 4, 3 to 8, 74138, Binary, Priority, BCD to 7 Segment, Digital Logic, Lecture Slides, Dr D J Jackson, Department of Electrical and Compu...

# Test Paper - Digital Logic Design and Application - Mumbai University - Computer Engineering - 3rd Semester - 2009

DeMorgan's theorem, K-map, NAND gate, TTL CMOS and ECL, Quine McClusky method, 4-bit universal shift register, Totem pole output stage of TTl gate, Priority encoder, Current and voltage parameters of logic gates, Race around condition in J-K Flip-...

# Johnson Counter by using Quartus II (64-bit)

How to design Johnson Counter by using Quartus II (64-bit)

# Binary to gray conversion

Digital logic design

# State Minimization-Digital Logic-Lecture 32 Slides-Electrical and Computer Engineering

Instead of trying to show which states are equivalent, it is often easier to show which states are definitely not equivalent. State Minimization, Finite State Machines, FSM, State Equivalence, 0 Successor, 1 Successor, k Successor, Partitioning Mi...

# Design Finite State Machines-Digital Logic-Lecture 31 Slides-Electrical and Computer Engineering

VHDL provides a number of constructs for designing finite state machines. Design Finite State Machines, CAD Tools, FSM, Data Type, Type, Representing States, Moore State, VHDL, Mealy, 11 Detector, Digital Logic, Lecture Slides, Dr D J Jackson, Dep...

# VHDL for Sequential Circuits-Digital Logic-Lecture 30 Slides-Electrical and Computer Engineering

VHDL for Sequential Circuits, D Flip Flop, Package, Active Low Signal, Gated D Latch, Code, Positive Edge Triggered, Synchronous Reset, MUX Input, Four Bit Shift Register, Up Counter, Digital Logic, Lecture Slides, Dr D J Jackson, Department of El...