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**No. 2-1
**

**Chapter #2: Two-Level Combinational Logic**

**No. 2-2
**

**Motivatio
n
**

* Rapid prototyping technology
*

** Use of computer aided design tools: espresso
**

* Design Techniques that Spanning Multiple Technologies
*

** Transistor-Transistor Logic (TTL)
**

** Complementary Metal on Oxide Silicon (CMOS)
**

* Multiple Design Representations
*

** Truth Tables
**

** Static gate descriptions
**

** Dynamic waveform descriptions
**

*Further Amplification on the Concepts of Chapter #1:*

**No. 2-3
**

**Chapter Overview
**

* Logic Functions and Switches
*

** Not, AND, OR, NAND, NOR, XOR, XNOR
**

* Gate Logic
*

** Laws and Theorems of Boolean Algebra
**

** Two Level Canonical Forms
**

** Incompletely Specified Functions
**

* Two Level Simplification
*

** Boolean Cubes
**

** Karnaugh Maps
**

** Quine-McClusky Method
**

** Espresso Method
**

**No. 2-4
**

**Logic Functions: Boolean Algebra
**

**is Algebraic structure consisting of:
**

** set of elements B
**

** binary operations {+, •}
**

** unary operation {'}
**

**such that the following axioms hold:
**

**1. B contains at least two elements, a, b, such that a ≠ b
**

**2. Closurea,b in B,
(i) a + b in B
(ii) a • b in B
**

**3. Commutative Laws: a,b in B,
(i) a + b = b + a
(ii) a • b = b • a
**

**4. Identities: 0, 1 in B
(i) a + 0 = a
(ii) a • 1 = a
**

**5. Distributive Laws:
(i) a + (b • c) = (a + b) •(a + c)
(ii) a •(b + c) = a b + a • c
**

**6. Complement:
(i) a + a' = 1
(ii) a • a' = 0**

**No. 2-5
**

**Logic Functions: Boolean Algebra
Note that B = {0,1}, + = OR, • = AND, ' = NOT is a Boolean Algebra
**

**must verify that the axioms hold:
E.g., Commutative Law:
**

**0 + 1 = 1 + 0
1 = 1
**

**0 • 1 = 1 • 0
0 = 0
**

**Theorem: any Boolean function that can be expressed as a truth table
can be written as an expression in Boolean Algebra using ', +, •
**

*Review
from
*

*Chapter 1
*X Y

*Description
*Z = 1 if X and Y
are both 1

*Gates Truth Table Switches
*X
Y Z

**Y
0
1
0
1
**

**X
0
0
1
1
**

**Z
0
0
0
1
**

**X • Y
**

*false
*

*true
*

**NOT
**

**AND
**

**OR
**

Description If X = 0 then X ' = 1 If X = 1 then X ' = 0

Switches Gates

X

X X 0 1

X 1 0

T ruth T able

X T rue

False X

Description Z = 1 if X or Y (or both) are 1

Gates T ruth T able Switches X Y Z

X 0 0 1 1

Y 0 1 0 1

Z 0 1 1 1

X Y

X + Y

False

T rue

**No. 2-6
**

**Logic Functions: From Expressions to
GatesMore than one way to map an expression to gates
**

**E.g., Z = A' • B' •(C + D) = (A' •(B' •(C + D)))
T1
**

**T2
**

*Literal*: each appearance of a variable or its complement in an expression
E.g., Z = A B' C + A' B + A' B C' + B' C

**use of 3-input gate
**

**3 variables, 10 literals
**

A

B

C

D T

2

T 1

Z

Z

A

B

C

D

**No. 2-7
**

Description Z = 1 if X is 0 or Y is 0

Gates T ruth T able Switches

X Y

X • Y

False

T rue X 0 0 1 1

Y 0 1 0 1

Z 1 1 1 0

X Y Z

F0 0 0 0 0

F1 0 0 0 1

F2 0 0 1 0

F3 0 0 1 1

F4 0 1 0 0

F5 0 1 0 1

F6 0 1 1 0

F7 0 1 1 1

F8 1 0 0 0

F9 1 0 0 1

F10 1 0 1 0

F1 1 1 0 1 1

F12 1 1 0 0

F13 1 1 0 1

F14 1 1 1 0

F15 1 1 1 1

X 0 0 1 1

Y 0 1 0 1

0 X • Y X Y X + Y X Y

1

**Logic Functions: NAND, NOR, XOR,
XNOR
16 functions of two variables:
**

**X, X', Y, Y', X • Y, X+Y, 0, 1 only
half of the possible functions
**

**NAND
**

**NOR
**Description
Z = 1 if both X
and Y are 0

Gates T ruth T able Switches X Y

Z X 0 0 1 1

Y 0 1 0 1

Z 1 0 0 0

X Y

X + Y False

T rue

**No. 2-8
**

**Logic Functions: NAND, NOR
Implementation
**

**NAND, NOR gates far outnumber AND, OR in typical designs
easier to construct in the underlying transistor technologies
**

**Any Boolean expression can be implemented by NAND, NOR, NOT gates
**

**In fact, NOT is superfluous
(NOT = NAND or NOR with both inputs tied together)
**

**X
0
**

**1
**

**Y
0
**

**1
**

**X NOR Y
1
**

**0
**

**X
0
**

**1
**

**Y
0
**

**1
**

**X NAND Y
1
**

**0**

**No. 2-9
**

**Logic Functions: XOR,
XNOR
XOR: X or Y but not both ("inequality", "difference")
XNOR: X and Y are the same ("equality", "coincidence")
**

**X Y = X Y' + X' Y X Y = X Y + X' Y'
**

(a) XOR (b) XNOR

Description Z = 1 if X has a different value than Y

Gates

T ruth T able

X

Y Z

X 0 0 1 1

Y 0 1 0 1

Z 0 1 1 0

Description Z = 1 if X has the same value as Y

Gates

T ruth T able

X Y

Z

X 0 0 1 1

Y 0 1 0 1

Z 1 0 0 1

**No. 2-10
**

**Logic Functions: Waveform View**

**No. 2-11
**

**Logic Functions: Rationale for
Simplification
**

**Logic Minimization: reduce complexity of the gate level implementation
**** reduce number of literals (gate inputs)
**

** reduce number of gates
**

** reduce number of levels of gates
**

**fewer inputs implies faster gates in some technologies
**

**fan-ins (number of gate inputs) are limited in some technologies
**

**fewer levels of gates implies reduced signal propagation delays
**

**minimum delay configuration typically requires more gates
**

**number of gates (or gate packages) influences manufacturing costs
**

*Traditional methods:
*reduce delay at expense of adding gates

*New methods:
*trade off between increased circuit delay and reduced gate count

*Traditional methods:
*reduce delay at expense of adding gates

*New methods:
*trade off between increased circuit delay and reduced gate count

**No. 2-12
**

**Logic Functions: Alternative Gate Realizations
**

**Two-Level Realization
(inverters don't count)
**

**Multi-Level Realization
Advantage: Reduced Gate
**

**Fan-ins
**

**Complex Gate: XOR
Advantage: Fewest Gates
**

**Number of gates:
Z1 - 3x inverters, 3x 3-input AND, 1x 3-input OR
Z2 - 2x inverters, 3x 2-input AND, 1x 2-input OR
Z3 - 1x 2-input AND, 1x 2-input XOR
**

0 1 0 1 0 1

A B C

0

0

Z 1

Z 2

Z 3

0

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Z 0 1 0 1 0 1 1 0

**No. 2-13
**

**Logic Functions: Waveform Verification
**

**Under the same input stimuli, the three alternative implementations have
essentially the same waveform behavior.
**

**Slight delay variations due to differences in number of gate levels
**

**The three implementations are equivalent
**

**There are some glitches in all of them!**

**No. 2-14
**

**Gate Logic: Laws of Boolean Algebra
**

**Duality: a dual of a Boolean expression is derived by replacing AND
operations by ORs, OR operations by ANDs, constant 0s by 1s, and
1s by 0s (literals, I.e., inputs are left unchanged).
**

*Any statement that is true for an expression is also true for its dual!
*

**Useful Laws/Theorems of Boolean Algebra:
Operations with 0 and 1:
**

*Idempotent Law:
*

*Involution Law:
*

*Laws of Complementarity:
*

*Commutative Law:
*

**1. X + 0 = X
2. X + 1 = 1
**

**1D. X • 1 = X
2D. X • 0 = 0
**

**3. X + X = X 3D. X • X = X
**

**4. (X')' = X
**

**5. X + X' = 1 5D. X • X' = 0
**

**6. X + Y = Y + X 6D. X • Y = Y • X**

**No. 2-15
**

**Gate Logic: Laws of Boolean Algebra (cont)
**

*Distributive Laws:
*

*Simplification Theorems:
*

*DeMorgan's Law:
*

*Duality:
*

*Theorems for Multiplying and Factoring:
*

*Consensus Theorem:
*

**8. X •(Y+ Z) = (X • Y) + (X • Z) 8D. X + (Y • Z) = (X + Y) •(X + Z)
**

**9. X • Y + X • Y' = X
10. X + X • Y = X
11. (X + Y') • Y = X • Y
**

**9D. (X + Y) • (X + Y') = X
10D. X •(X + Y) = X
11D. (X • Y') + Y = X + Y
**

**12. (X + Y + Z + ...)' = X' • Y' • Z' •...
13. {F(X1,X2,...,Xn,0,1,+, •}' = {F(X1',X2',...,Xn',1,0, • +)}
**

**12D. (X • Y • Z •...) ' = X' + Y' + Z' + ...
**

**14. (X + Y + Z + ...) = X • Y • Z •...
**

**15. {F(X1,X2,...,Xn,0,1,+, •} = {F(X1,X2,...,Xn,1,0, • +)}
**

**D
**

**D
14D. (X • Y • Z •...) = X + Y + Z + ...D
**

**16. (X + Y) •(X' + Z) = X • Z + X' • Y 16D. X • Y + X' • Z = (X + Z) •(X' + Y)
**

**17. (X • Y) + (Y • Z) + (X' • Z) =
X • Y + X' • Z
**

**17D. (X + Y) •(Y + Z) •(X' + Z) =
(X + Y) •(X' + Z)
**

*Associative Laws:
*7. (X + Y) + Z = X + (Y + Z)
= X + Y + Z

**7D. (X • Y) • Z = X •(Y • Z)
= X • Y • Z**

**No. 2-16
**

**Gate Logic: Laws of Boolean Algebra
Proving theorems via axioms of Boolean Algebra:
**

**E.g., prove the theorem: X • Y + X • Y' = X
**

**E.g., prove the theorem: X + X • Y = X
**

** X • (Y +Y')=X
= X •1
= X
**

**dist, law 8
complementarity theorem 5
identity (1D)
**

** X •1+ X •Y
= X • (1+Y)
= X •1
= X
**

**identity 1D
dist
identity 2
identity 1D **

**No. 2-17
**

**Gate Logic: Laws of Boolean Algebra
Proving theorems via axioms of Boolean Algebra:
**

**E.g., prove the theorem: X • Y + X • Y' = X
**

** X • Y + X • Y' = X •(Y + Y')
**

** X •(Y + Y') = X •(1)
**

** X •(1) = X
**

*distributive law (8)
*

*complementary law (5)
*

*identity (1D)
*

**E.g., prove the theorem: X + X • Y = X
X + X • Y = X • 1 + X • Y
**

**X • 1 + X • Y = X •(1 + Y)
**

**X •(1 + Y) = X •(1)
**

**X •(1) = X
**

*identity (1D)
*

*distributive law (8)
*

*identity (2)
*

*identity (1)*

**No. 2-18
**

**Gate Logic: Laws of Boolean Algebra
DeMorgan's Law
**

**(X + Y)' = X' • Y'
**

**(X • Y)' = X' + Y'
**

**NOR is equivalent to AND
with inputs complemented
**

**NAND is equivalent to OR
with inputs complemented
**

**Example:
Z = A' B' C + A' B C + A B' C + A B C'
**

**Z' = (A + B + C') • (A + B' + C') • (A' + B + C') •(A' + B' + C)
**

**DeMorgan's Law can be used to convert AND/OR expressions
to OR/AND expressions
**

**DeMorgan's Law can be used to convert AND/OR expressions
to OR/AND expressions
**

X 0 0 1 1

Y 0 1 0 1

X 1 1 0 0

Y 1 0 1 0

X + Y 1 0 0 0

X**•**Y
1
0
0
0

X 0 0 1 1

Y 0 1 0 1

X 1 1 0 0

Y 1 0 1 0

X + Y 1 1 1 0

X**•**Y
1
1
1
0

**No. 2-19
**

**Gate Logic: Laws of Boolean Algebra
**

*Apply the laws and theorems to simplify Boolean equations
*

**Example: full adder's carry out function
Cout = A' B Cin + A B' Cin + A B Cin' + A B Cin**

**No. 2-20
**

**Gate Logic: Laws of Boolean Algebra
**

*Apply the laws and theorems to simplify Boolean equations
*

**Example: full adder's carry out function
Cout = A' B Cin + A B' Cin + A B Cin' + A B Cin
**

**= A' B Cin + A B' Cin + A B Cin' + A B Cin + A B Cin
**

**= A' B Cin + A B Cin + A B' Cin + A B Cin' + A B Cin
**

**= (A' + A) B Cin + A B' Cin + A B Cin' + A B Cin
**

**= (1) B Cin + A B' Cin + A B Cin' + A B Cin
**

**= B Cin + A B' Cin + A B Cin' + A B Cin + A B Cin
**

**= B Cin + A B' Cin + A B Cin + A B Cin' + A B Cin
**

**= B Cin + A (B' + B) Cin + A B Cin' + A B Cin
**

**= B Cin + A (1) Cin + A B Cin' + A B Cin
**

**= B Cin + A Cin + A B (Cin' + Cin)
**

**= B Cin + A Cin + A B (1)
**

**= B Cin + A Cin + A B
**

*identity
*

*associative*

**No. 2-21
**

A + 0 = A A + 1 = 1

A A

0

=

A 1

= 1

**Gate Logic: Switching
Equivalents
**

**Idempotent Laws Identity Laws
**

**Complementarity Laws Simplification Theorems
**

A • A = A

A A A

A

A

A + A = A

= =

A

A + A = 1 A • A = 0

A

A =

1

A A

=

0

X Y + X Y = X X + X Y = X

X Y

X Y

X Y

X

= =

X X

**No. 2-22
**

**Gate Logic: 2-Level Canonical
Forms
**

**Truth table is the unique signature of a Boolean function
**

**Many alternative expressions (and gate realizations) may have the same
truth table
**

**Canonical form: standard form for a Boolean expression
provides a unique algebraic signature
**

*Sum of Products Form
*also known as disjunctive normal form, minterm expansion

**F = A' B C + A B' C' + A B' C + A B C' + A B C
0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
**

**F' = A' B' C' + A' B' C + A' B C'
**

F 0 0 0 1 1 1 1 1

F 1 1 1 0 0 0 0 0

C 0 1 0 1 0 1 0 1

B 0 0 1 1 0 0 1 1

A 0 0 0 0 1 1 1 1

**No. 2-23
**

**Gate Logic: Two Level Canonical Forms
**

*Sum of Products
*

**Shorthand Notation for
Minterms of 3 Variables
**

*minterm:
*ANDed product of literals in which each
variable appears exactly once, in true or
complemented form (but not both!)

*F in canonical form:
*

**F(A,B,C) = ****m(3,4,5,6,7)
= m3 + m4 + m5 + m6 + m7
= A' B C + A B' C' + A B' C
+ A B C' + A B C
**

*Minimized gate-level implementation
*F = A B' (C + C') + A' B C + A B (C' + C)

**= A B' + A' B C + A B
**

**= A (B' + B) + A' B C
**

**= A + A' B C
**

**= A + B C
2-Level AND/OR
**

**Realization F' = (A + B C)' = A' (B' + C') = A' B' + A' C'
**

B

C

A

F

A B C = m 1 A B C = m 2 A B C = m 3 A B C = m 4 A B C = m 5 A B C = m 6 A B C = m 7

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Minterms A B C = m 0

**product
terms
**

** Minterm **

*product term***No. 2-24
**

**Gate Logic: 2 Level Canonical
Forms Product of Sums / Conjunctive Normal Form / Maxterm Expansion
**

**Maxterm Shorthand Notation
for a Function of Three Variables
**

*Maxterm:
*ORed sum of literals in which each
variable appears exactly once in either
true or complemented form, but not both!

*Maxterm form:
*Find truth table rows where F is 0
0 in input column implies true literal
1 in input column implies complemented
literal

**F(A,B,C) = ****M(0,1,2)
= (A + B + C) (A + B + C') (A + B' + C)
**

**F'(A,B,C) = ****M(3,4,5,6,7)
= (A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')
**

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Maxterms A + B + C = M 0 A + B + C = M 1 A + B + C = M 2 A + B + C = M 3 A + B + C = M 4 A + B + C = M 5 A + B + C = M 6 A + B + C = M 7

**No. 2-25
**

**Gate Logic: Two Level Canonical Forms
Sum of Products, Products of Sums, and DeMorgan's Law
**

**F' = A' B' C' + A' B' C + A' B C'
Apply DeMorgan's Law to obtain F:
**

**(F')' = (A' B' C' + A' B' C + A' B C')'
**

**F = (A + B + C) (A + B + C') (A + B' + C)
**

**F' = (A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')
**

**(F')' = {(A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')}'
F = A' B C + A B' C' + A B' C + A B C' + A B C
**

**Apply DeMorgan's Law to obtain F:**