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Specification ALU (Arithmetic Logic Unit) performs 16 different operations, including
• Logic operations • Arithmetic operations • Shifts and rotations • BCD (Binary Coded Decimal) to binary conversion.
The following diagram shows the interface of this circuit.
The following table gives the name, meaning and width of each port.
Name Mode Width Meaning CLK INPUT 1 Clock RST INPUT 1 Reset (active high)
FETCH INPUT 1 Signal indicating that an opcode is ready at the input OPCODE, and should be read at the next rising edge of the clock.
A INPUT 8 Input A B INPUT 8 Input B
OPCODE INPUT 4 Operation Code X OUTPUT 8 Output or Least Significant
Byte of Output Y OUTPUT 8 Most Significant Byte of
Output (used in 3 operations only)
C OUTPUT 1 Carry Flag N OUTPUT 1 Negative Flag V OUTPUT 1 Overflow Flag
BUSY OUTPUT 1 Busy indicator. Set to 1 for one clock cycle after FETCH is detected.
Each operation performed by ALU has a specific OPCODE as shown in the table below. C, N, V are one-bit flags (registers). They are either affected by a given operation, cleared, or remain unchanged, as summarized in the last three columns of the table. The general rules are summarized below:
• Logic operations clear the overflow bit V. • Unsigned and logic operations clear the negative flag N. • Unsigned addition and subtraction affect the carry flag C.
C is set when the result is out of range for 8-bit unsigned numbers, i.e., either smaller than 0, or greater than 255, and is cleared otherwise.
• The results of signed and unsigned multiplications can always be represented using 16 bits stored in registers Y:X (with Y representing 8 most significant bits, and X representing 8 least significant bits of the result).
• Rotation with carry affects C. The carry flag, C, is changed to the value of the bit rotated to C.
OPCODE OPERATION FORMULA V C N 0000 NOR X = A NOR B 0 − 0 0001 NAND X = A NAND B 0 − 0 0010 XOR X = A XOR B 0 − 0 0011 Unsigned Addition (C:X) = A + B − ↕ 0
0100 Signed Addition X = A + B ↕ − ↕ 0101 Unsigned Addition with
Carry (C:X) = A + B +
C − ↕ 0
0110 Signed Subtraction X = A - B ↕ − ↕ 0111 Unsigned Multiplication (Y:X) = A * B − − 0 1000 Signed Multiplication (Y:X) = A * B − − ↕ 1001 Variable Rotation Right X = A >>> B − − − 1010 Variable Logic Shift Left X = A << B
(logic shift) − − −
1011 Rotation Right with Carry (C:X) = (C:A) >>> 1
− ↕ −
1100 Variable Arithmetic Shift Right with Rounding
X = (A >> B) + AB-1 (arithmetic
− − ↕
1101 Variable Logic Shift Right X = A >> B (logic shift)
− − −
1110 Variable Arithmetic Shift Left
X = A << B (arithmetic shift)
↕ − −
1111 BCD to Binary Conversion (Y:X) = BCD2BIN(B:A)
− − −
The notation used in the table is as follows: (Y:X) denotes concatenation of Y and X, with the most significant part stored in Y, and the least significant part stored in X. ↕ means that a given flag is affected. − means that a given flag is unaffected. 0 means that a given flag is cleared. A <<< B = rotation of A left by the number of positions given by a value of B. A << B = shift of A left by the number of positions given by a value of B. X = (A >> B) + AB-1 = An arithmetic shift by the number of positions given by B followed by a rounding operation, which consists of adding the value of the B-1st bit of A to the result of the shift. BCD2BIN(B:A) = conversion of a 4-digit decimal value encoded in BCD (binary-coded decimal) to a binary value. The input may vary between 0000 and 9999 (decimal). 4 bits are used to represent each decimal digit in BCD. Each instruction requires two clock cycles to execute. The execution starts at the first rising edge after OPCODE is set to the desired value, and FETCH is set to 1. During the following clock cycle BUSY is set to 1. When BUSY is set to 1, FETCH is ignored.
The PostSynthesis Simulation Model of ALU is provided to you as alu_synthesis.vhd. Your task is to verify that this model implements the ALU circuit in agreement with the specification. To make your task more challenging, the provided model contains several discrepancies compared to the specification. These discrepancies may have for example the following forms:
a. Performed operation does not match its opcode. b. Operation affects flags or registers that should be left unchanged. c. The result of the operation is incorrect for a subset of operand values.
Swapping opcodes of two operations is a special case of a., and should be counted as two discrepancies. The provided model contains a total of 14 known discrepancies. Your task is to find and document all of them. Task 1 Write a testbench capable of verifying the operation of the provided model and detecting all discrepancies. The input stimuli and expected output vectors should be stored in an array of records in your testbench. The array must contain at least two test vectors per each ALU operation (i.e., at least 32 test vectors total). The testbench should detect any discrepancies with the specification, and print messages describing all detected errors to the standard output using the instruction ASSERT or REPORT. Task 2 Write a program in a high-level programming language (e.g., C, C++, Java, Perl, Python) that generates comprehensive test vectors for the ALU circuit. All test vectors should be stored in a text file using the following format: A B OPCODE X N C V [Y] where
• A, B, OPCODE are inputs, generated at random • X, N, C, V, Y are corresponding expected outputs, and Y is optional • A, B, OPCODE, X, and Y are given in the hexadecimal notation, and N, C, V are
represented using a single character = 0, 1, or −, where – means unaffected. • Space is used as a separator.
For example, the following lines are valid test vector file lines: 40 80 7 00 0 − − 20 C8 B4 2 7C 0 − 0 The program should generate N lines, where N is an argument provided by the user (e.g., N=128). All flags should be assumed to be cleared by the reset at the beginning of simulation. All inputs should be selected using a pseudo-random number generator.
Task 3 Develop an advanced testbench in VHDL to test and verify the operation of the ALU model using test vector file generated in Task 2. Each time the discrepancy is detected, it should be clearly reported by the testbench as an error message. Hint: It is recommended that all data and control inputs provided to the circuit under test by both testbenches are changed at the falling edges of the clock. Task 4 Write a short report describing all discrepancies you have found and test vectors capable of detecting them. Deliverables:
1. VHDL code of the testbenches developed in Tasks 1 and 3. 2. High level programming language code developed in Task 2. 3. Test vector file generated by the program developed in Task 2, used by the
testbench developed in Task 3. Assume using the number of test vectors N=128. 4. Messages written to standard output by running testbenches developed in Tasks 1
and 3. 5. Waveforms obtained by applying your testbenches developed in Tasks 1 and 2.
You can use an arbitrary simulator available to you at home or at GMU. All timing waveforms should be provided in the form of PDF files.
6. Report developed in Task 4.