Basic Code Generation, DAG Representations - Compiler Construction - Lecture Slides, Slides for Compiler Construction. Birla Institute of Technology and Science
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Basic Code Generation, DAG Representations - Compiler Construction - Lecture Slides, Slides for Compiler Construction. Birla Institute of Technology and Science

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Basic Code Generation, Data Flow Analysis, Variables, DAG Representations, Interior nodes, Optimization, Labeling algorithms are basic concepts discussed of course.
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What is a compiler?

Compiler Construction

Lecture 45

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Liveness information allows us to keep values in registers if they will be used later (efficiency)

Basic Code Generation

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 Why do we assume all variables are live at the end of blocks?  Can we do better?

Basic Code Generation

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 Why do we need to save live variables at the end?  We might have to reload

them in the next block.  Global Data-Flow Analysis

Basic Code Generation

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DAG Representations A dag (directed acyclic graph) for a basic block has the following labels for the nodes:

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DAG Representations  Leaves are labeled by

unique identifiers.  Interior nodes are labeled by

operator symbols.  Nodes can have multiple

labels since they represent computed values.

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DAG Representations BB DAG for x = y op z

op x

y z

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Generating DAGs For statement i: x = y op z  if y op z node exists,

add x to the label for that node. else

add node for y op z.  If y or z exist in the dag,

point to existing locations else

add leaves for y and/or z and have the op node point to them.

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Generating DAGs  Label the op node with x.

 If x existed previously as a leaf, subscript that previous entry.

 If x is associated with other interior nodes, remove them from that list.

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Example 1 a = b + c t1 = a * a b = t1 + a c = t1 * b t2 = c + b a = t2 + t2

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Example 1 a = b + c t1 = a * a b = t1 + a c = t1 * b t2 = c + b a = t2 + t2 b c

+ a

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Example 1 a = b + c t1 = a * a b = t1 + a c = t1 * b t2 = c + b a = t2 + t2 b

t1

c

+

*

a

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Example 1 a = b + c t1 = a * a b = t1 + a c = t1 * b t2 = c + b a = t2 + t2 b’

t1

c

+

*

+ b

a

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Example 1 a = b + c t1 = a * a b = t1 + a c = t1 * b t2 = c + b a = t2 + t2 b’

t1

c’

+

*

+ b

* c

a

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Example 1 a = b + c t1 = a * a b = t1 + a c = t1 * b t2 = c + b a = t2 + t2 b’

t1

c’

t2

+

*

+ b

* +

c

a

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Example 1 a = b + c t1 = a * a b = t1 + a c = t1 * b t2 = c + b a = t2 + t2 b’

t1

c’

t2

+

*

+ b

*

+

+

c

a

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Example 2 t1 = 4 * i t2 = a[t1] t3 = 4 * i t4 = b[t3] t5 = t2 * t4 t6 = p + t5 p = t6 t7 = i + 1 i = t7 if i <20 goto (1)

a b 4 i’ 1

+ *

< [ ] [ ]

*

+

p’

t6,p

t5

t2 t4

t1,t3 t7,i

(1)

20

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DAGs and optimization  Detect common sub-expression

elimination. Node with more than one parent is common sub-expression

 Reordering to reduce number of generated instructions • node listing • labeling algorithms

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Order Matters

Order 1 t1 = a + b t2 = c + d t3 = e – t2 t4 = t1 – t3

Order 2 t2 = c + d t3 = e – t2 t1 = a + b t4 = t1 – t3

+ a b e

c d

t2

t3

t4

t1

-

- +

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Order #1 with 2 registers t1 = a + b t2 = c + d t3 = e – t2 t4 = t1 – t3

MOV a, R0 ADD b,R0 MOV c, R1 ADD D, R1 MOV R0,t1 MOV e, R0 SUB R1,R0 MOV t1,R1 SUB R0, R1 MOV R1,t4 ; 10 instructions Docsity.com

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Order #2 with 2 registers t2 = c + d t3 = e – t2 t1 = a + b t4 = t1 – t3

MOV c, R0 ADD D, R0 MOV e, R1 SUB R0,R1 MOV a,R0 ADD b, R0 MOV R0,t4 ; 7 instructions

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Order 1 t1 = a + b t2 = c + d t3 = e – t2 t4 = t1 – t3

Order 2 t2 = c + d t3 = e – t2 t1 = a + b t4 = t1 – t3

 Reordering improved code because computation of t4 immediately followed computation of t1, its left operand.  t1 must be in a register and it is

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Optimal Ordering Algorithms

 Heuristic ordering algorithm: node listing Ordering when DAG for a block is

a tree  Both algorithms presented in the

book

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Register Allocation  How to best use the bounded

number of registers.

 Local register allocation: graph coloring problem.

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Register Allocation Complications: • special purpose registers • operators requiring multiple

registers.

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