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**5-1
**

Design of Basic Computer The basic computer consists of the following hardware components

1. A memory unit with 4096 words of 16bits 2. Nine registers : AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC 3. Seven F/Fs : I, S, E, R, IEN, FGI, and FGO 4. Two decoder in control unit : 3 x 8 operation decoder, 4 x 16 timing

decoder
5. A 16-bit common bus
** 6. Control Logic Gates **:

*7. Adder and Logic circuit connected to the AC input* Control Logic Gates 1. Signals to control the inputs of the nine registers 2. Signals to control the read and write inputs of memory 3. Signals to set, clear, or complement the F/Fs 4. Signals for S2 S1 S0 to select a register for the bus 5. Signals to control the AC adder and logic circuit

**5-2
**

AR

LD

T2

T3 D'7

Clock CLRINR

To BusFrom Bus 12 12

I

R

T4

D5

T0

**5-3
**

Register Control : AR
Control inputs of AR : ** LD, INR, CLR
**

*Find all the statements that change the AR*** in Tab. 5-6
** Control functions

Memory Control : READ
Control inputs of Memory : ** READ, WRITE
** Find all the statements that specify a

**in Tab. 5-6 Control function**

*read operation* F/F Control : IEN Control functions

?*AR
*

1: 0:

][:' )110(:'

:'

45

0

37

1

0

*ARARTD
ARRT
*

*ARMARITD
IRARTR
PCARTR
*

45

0

3710

)( )(

''')(

*TDARINR
RTARCLR
*

*ITDTRTRARLD
*

][? *ARM*

43210371 )('' *TDDDDITDTRREAD *

?][ *ARM
*

?*IEN
*

0: 0: 1:

2

6

7

*IENRT
IENpB
IENpB
*

T3 D'7 I

B7

R T2

Clock

J

*Q
*

*Q
*

K

SET

CLR

IEN

p

B6

**J K
0 1
1 0 1
**

**Q(t+1)
0**

**5-4
**

Bus Control
Encoder for Bus Selection : *Tab. 5-7
*

» S0 = x1 + x3 + x5 + x7 » S1 = x2 + x3 + x6 + x7 » S0 = x4 + x5 + x5 + x7

x1 = 1 : »

» Control Function : x2 = 1 :

x7 = 1 : » Same as Memory Read » Control Function :

»

*ARFindARBus * ?

*ARPCTD
ARPCTD
*

: :

55

44

55441 *TDTDx *

*PCFindPCBus * ?

][? *ARMFindMemoryBus *

432103717 )('' *TDDDDITDTRx *

“

“

Encoder Multiplexer Bus Select

Input

**x1
x2
x3
x4
x5
x6
x7
**

**S0
S1
S2**

**5-5
**

Design of Accumulator Logic

Adder and logic circuit

Accumulator register

(AC)

Control gates

INRLD CLR Clock

From DR To Bus

From INPR

16

16

16 16

8

Circuits associated with Accumulator

**5-6** Control of AC Register :

1: 0:

)0(,: )15(,:

:

)70(: : : :

5

11

6

7

9

11

52

51

50

*ACACrB
ACrB
*

*EACACshrACrB
EACACshrACrB
*

*ACACrB
*

*INPRACpB
DRACTD
*

*DRACACTD
DRACACTD
*

**LD
**

**INR
**

**CLR
**

*shl
*

**AND with DR
**

**ADD with DR
**

**Transfer from DR
**

**Transfer from INPR
**

**Complement
**

**Shift right
**

**Shift left
**

**Clear
**

**Increment
**

**Memory
reference
**

**Register reference
**

**I/O reference**

**5-7
**

AC

LD

T5 D0

Clock CLRINR

To BusFrom adderand logic

16 16

p

B11

D1

T5 D2

r

B9

B5

B6

B7

B11

AND

COM

INPR

DR

ADD

INC

SHL

SHR

CLR

Gate Structure for Controlling LD, INR, CLR & AC

**The control function for the clear operation is rB11 where r=D7I’T3 AND B11 =IR(11).**

**5-8
**

Adder and Logic Circuit : *The adder and logic circuit is devided into 16
stages with each stage corresponding to one bit of AC.
*

** Each stage has a JK flip flop, 2 OR gate , and two AND gate.
**

*The LD input is connected to the input of AND Gate.* *Note: one stage of Adder and logic ckt consist of seven AND Gate, One
OR Gate and a FULL ADDER(FA).
*

*The AND operation is achieved with ANDing AC( i) with the
corresponding bit in the DR(i).*

**5-9
**

AND

COM

INPR

DR

ADD

SHL

SHR

FA J Q

K

LD (Output of OR gate in Fig. 5- 20)

(Fig.2- 11)Ii AC(i)

Clock

AC(i- 1)

AC(i+1)

From INPR bit(i)

Ci+1

Ci

DR(i) AC(i)

**J K
0 1
1 0 1
**

**Q(t+1)
0**