# Catalog Search Circuit - Digital System Design with VHDL - Homework, Exercises for Digital Systems Design

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Homework for Digital System Design with VHDL course. Solve it, it will be helpful for your exam preparation. Its questions are about: Catalog Search Circuit, Text Description, Pseudocode, Output Ports, Pseudocode, Interf...
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Problem 1 Specification: The CATALOG_SEARCH circuit is specified below using its:

1. Text description 2. Pseudocode 3. Table of input/output ports 4. Timing requirements.

1. Text description The CATALOG_SEARCH circuit takes as an input a stream of 8-bit ASCII characters representing a GMU catalog. It searches for the first 32 instances of the string “GMU”. Then, it calculates an average and maximum distance between the two subsequent repetitions of this string (including the distance between the first instance of the string and the beginning of the catalog). 2. Pseudocode In the code below, MEM_D represents RAM of the size of 32 x 16. begin: wait for s=1 done = 0 count = 0 first = SPACE second = SPACE third = SPACE last = 0 sum=0 max=0 i=-2 while (count < 32) do first = second second = third third =din if ((first = ‘G’) and (second = ‘M’) and (third = ‘U’)) then dist = i - last last = i sum = sum + dist if max < dist then max = dist end if;

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MEM_D[count] = dist count ++; end if; i++ end while avr = sum/32 done = 1 wait for s=0 // when s=0, an external circuit can read data from memory MEM_D, one number at a time, // using ports mem_addr and mem_dout go to begin 3. Table of input/output ports

Port Width Meaning clk 1 System clock.

reset 1 System reset – clears all internal registers and counters. Active high.

din 8 Input data bus. s 1 Operating mode: 0 = waiting for data / reading results,

1 = processing. rd 1 Read enable. 0 = high impedance on the output bus dout, 1 =

valid output dout. dout 16 One of the two results calculated by the circuit.

sel_out 1 Selection between the two calculated results: 0 = avr, 1 = max. mem_addr 5 Address in memory location MEM_D. mem_dout 16 High impedance (if s=1) or value of memory location

MEM_D[mem_addr] (if s=0). done 1 Asserted when all results are ready, zero otherwise.

4. Timing requirements The circuit should process one catalog character per clock cycle. Tasks: Task 1 Draw a block diagram of the Datapath of the CATALOG_SEARCH circuit. Use medium complexity components corresponding to the operations used in the pseudocode. Clearly specify

names, widths and directions of all buses names, widths and directions of all inputs and outputs of the logic components.

Task 2 Draw an interface of the CATALOG_SEARCH circuit with the division into the Datapath and Controller.

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Problem 2 Specification: The key scheduling unit of the RC5 cipher is a circuit that takes a 128-bit key K, and converts it to 2r+2 round keys S[i], i=0..2r+1, stored in the internal memory S[i]. This unit is specified below using its

1. pseudocode 2. interface 3. table of input/output ports.

1. Pseudocode The RC5 key scheduling unit is defined using the given below pseudocode. The input key K consists of four words K[0], K[1], K[2], and K[3], each of the size of 32 bits. These words are first written to the internal memory L[j], j=0..3, using the control signal write_key (active high) and the key input Kin. This process is described using the first for-loop of the pseudocode. Afterwards, the remaining part of the pseudocode is executed by the controller. P32 and Q32 are 32-bit constants. r is a parameter of RC5, with the default value of 12. for j = 0 to 3 do while (not write_key) do_nothing end while L[j] = Kin end for S[0] = R = P32 for i=1 to 2r+1 do S[i] = R = R + Q32 end for i = j = 0 A = B = 0 for k=1 to 3·(2r+2) do A’ = S[i] = (S[i] + A + B) <<< 3 B’ = L[j] = (L[j] + A’ + B) <<< (A’+B) A = A’ B = B’ i = (i+1) mod (2r+2) j = (j+1) mod 4 end for Notation: A, B, A’, B’ = 32-bit variables + = unsigned addition mod 232 X <<< Y = rotation of the variable X by a number of positions given by the current value of the variable Y Assume that you can use memories with the following inputs: ADDR, DIN, CLK, WE, and the output DOUT, which output data in the same clock cycle in which a new address is applied.

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Writing to memory takes effect at the rising edge of the clock when WE = 1. 2. Interface Assume the following interface to your circuit:

3. Table of input/output ports

Port Width Meaning clk 1 System clock.

reset 1 System reset – clears internal registers. write_key 1 Synchronous write control signal for the key input, Kin. Active

high. Kin 32 The key input, through which subsequent words of the key

K[0]..K[3] are loaded to the circuit. n m Index n of the round key S[n].

Sn 32 Value of the round key S[n] corresponding to the index provided through the input n.

Done 1 Asserted when the computations are completed. m is a size of index n. It is a minimum integer, such that 2m ≥ 2r+2. Task 1 Draw a block diagram of the Datapath. Assume that

one round of the main for loop of the pseudocode executes in one clock cycle you can access only one position of each internal memory per clock cycle after the circuit is done with computations, applying input n should generate value

of S[n] at the output Sn in the same clock cycle. Use medium complexity components corresponding to the operations used in the pseudocode. Clearly specify

names, widths and directions of all buses names, widths and directions of all inputs and outputs of the logic components.

Task 2 Draw an Interface of the circuit with the division into the Datapath and the Controller.

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