Designing 4-bit GCD Computer with Mentor Graphics Tools at Northwestern University, Study notes of Computer System Design and Architecture

Download Designing 4-bit GCD Computer with Mentor Graphics Tools at Northwestern University and more Study notes Computer System Design and Architecture in PDF only on Docsity! Northwestern University Oct 13, 2011 Electrical Engineering and Computer Science Handout #5 EECS 303: Advanced Digital Design, Fall 11 Due: Oct 20 Prof. Hai Zhou Lab 2 GCD Computer Design and Simulation 1 Introduction In this lab, you will use Mentor Graphics tools to design and simulate the GCD (Greatest Common Divisor) computer we discussed in class. The GCD computer computes the GCD of two positive numbers by using Euclid’s Algorithm–the first algorithm in history. It iteratively subtracts the smaller number from the larger one, until the two numbers are the same, which then gives the answer! Based on what we have discussed in the class, the logic diagram of the GCD computer for 2-bit numbers is shown in the following Figure 1. 2 Structured Design In this lab, we are going to design a GCD computer for 4-bit numbers that also include a way to set the input. The principle of structured design is to build larger components from smaller ones such that components can be reused. In order to design a 4-bit GCD computer, you may consider to first build a component for 1-bit GCD. The input of this component may include initial values “a” and “b”, clock, carry-ins “CI0” and “CI1”, and MUX selections “S0” and “S1”. It s output may have the carry-outs “CO0” and “CO1”. 3 Design and Simulation in Mentor Graphics Please first do your design on paper and make sure its correctness. After that, you need to put your design into the Mentor Graphics tools. There are D Flip-Flop, Full Adder, and MUX in the general library of the design tool, which you can use. Their names are dff, fa, and mux21, respectively. You may have noticed that the D flip-flop we are about to use is different from the one we see in class. This D flip-flop has two additional input ports: Preset and Clear. They are used to initialize the D flip-flop to input value. When Preset = 0 and Clear = 1, Q is set to 1 immediately regardless of the clock signal. Similarly, when Preset = 1 and Clear = 0, Q is set to 0. During the rest of GCD computing process, both Preset and Clear should be set to 1. Preset = Clear = 0 is forbidden. You may find a device called vcc in MGC library useful. It is basically the power supply and provides constant signal 1. After you put the design into the tool, please do the simulations on the following pairs of numbers. 1. 15 9 2. 11 8