Computer organisation, Lecture notes of Advanced Computer Architecture

Download Computer organisation and more Lecture notes Advanced Computer Architecture in PDF only on Docsity! Dept. of ISE, RNSIT 1 UNIT 6 ARITHMETIC Addition and subtraction are basic operations performed on digital computer. The Arithmetic and Logic Unit (ALU) performs these operations along with other logical operations like AND, OR, NOT, XOR. 6.1 Addition and Subtraction of Signed Numbers  Let X and Y be any two n bit numbers and xi and yi be the i th bit respectively in both numbers. Let Ci be the carry coming from (i – 1) thstage of addition of Xi-1 and Yi-1. The various possibilities are shown below: xi yi Carry-in Ci Sum Si Carry-out Ci+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1  Sum(Si) Logic If you notice carefully Sum (Si) bit is 1 (i.e. ON) in 4 scenarios. Scenario 1: xi = 0,yi=0 and Ci=1 i.e.x𝑖 𝑦𝑖 𝑐𝑖 Scenario 2: xi =0, yi=1 ,Ci=0 i.e. 𝑥𝑖 𝑦𝑖𝑐𝑖 Scenario 3: xi = 1, yi=0, Ci=0 i.e. 𝑥𝑖𝑦𝑖 𝑐𝑖 Scenario 4: xi = 1, yi= 1, Ci=1 i.e. 𝑥𝑖𝑦𝑖𝑐𝑖 Hence, Si =x𝑖 𝑦𝑖 𝑐𝑖 + 𝑥𝑖 𝑦𝑖𝑐𝑖 +𝑥𝑖𝑦𝑖 𝑐𝑖 +𝑥𝑖𝑦𝑖𝑐𝑖 (Note: The + refers to “OR” and not arithmetic „+‟) In short, Si = 𝒙𝒊  𝒚𝒊  𝒛𝒊 i.e. xi XOR yiXOR Ci  Carry (Ci) Logic You will notice that carry is 1 in following scenarios Scenario 1: xi = 0,yi=1 and Ci=1 i.e. 𝑥𝑖 𝑦𝑖𝑐𝑖 or 𝑦𝑖𝑐𝑖 Scenario 2: xi = 1,yi=0 and Ci=1 i.e. 𝑥𝑖𝑦𝑖 𝑐𝑖 or 𝑥𝑖𝑐𝑖 Scenario 3: xi = 1,yi=1 and Ci=0 i.e. 𝑥𝑖𝑦𝑖𝑐𝑖 or 𝑥𝑖𝑦𝑖 Scenario 4: xi = 1,yi=1 and Ci=1 i.e. 𝑥𝑖𝑦𝑖𝑐𝑖 Now, Scenario 3 and Scenario 4 can be shown by single equation i.e. 𝑥𝑖𝑦𝑖 Hence, carry is generated when 𝑐𝑖+1 = 𝑦𝑖𝑐𝑖 + 𝑥𝑖𝑐𝑖 + 𝑥𝑖𝑦𝑖  Circuits for Si and Ci+1 Both the above circuits can be put together and shown as a full adder (FA) as below: Figure 6.2a: Logic for a single stage UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 2 The above figure represents addition of two one bits. However, numbers are n bit long. Hence , a cascaded full adder is required to add two “n” bit number X and Y. Such a cascaded circuit where carry bit ripples from one FA to another is called a “n bit ripple-carry adder” as shown below. Figure 6.2b: An n-bit ripple-carry adder Suppose we need to add k such n bit number. (Ex If n=8 and we want to add two 32-bit numbers then we will need 4 such ripple address) So, a k n-bit adder is shown as: 6.1.1 Addition/Subtraction Logic Unit Addition: Addition of 2n bit numbers is fairly straight forward: Step 1: Obtain 2‟s complement of X (X is n bit numbers) Step 2: Obtain 2‟s complement of Y (Y is n bit numbers) Step 3: Use Fig 6.2 (b) to add these numbers. Co will be equal to 0 in this case. Xn-1 and Yn-1 shall be the sign bits (MSB)  Detecting overflow during Addition(Method 1) Let‟s recall showing when an overflow can occur: + 0 1 1 0 0 0 1 1  Sum is 1000 (There is an overflow as MSB bit is 1 for result) + 1 0 0 1 1 1 0 1  Sum is 0111 (There is an overflow as MSB bit is 0 for result) The problem with overflow is that the sum has a different sign compared to operands Note: Overflow is seen when xn-1 = 0, yn-1 = 0 and Sn-1 = 1 i.e. 𝑋𝑛−1 𝑌𝑛−1 𝑆𝑛−1 or xn-1 = 1, yn-1 = 1 and Sn-1 = 0 i.e.𝑋𝑛−1𝑌𝑛−1𝑆𝑛−1 A circuit to detect overflow can be written as: 𝑂𝑣𝑒𝑟𝑓𝑙𝑜𝑤 = 𝑋𝑛−1 𝑌𝑛−1 𝑆𝑛−1 + 𝑋𝑛−1𝑌𝑛−1𝑆𝑛−1  Detecting overflow during Addition (Method 2) If Carry(Cn-1) and Carry (Cn) are different then an overflow has occurred UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 5 We can recursively write Ci+1 as below Ci+1 = Gi + PiCi =Gi + Pi[Gi-1 + Pi-1Ci-1] =Gi + PiGi-1 + PiPi-1Ci-1 = Gi + PiGi-1 + PiPi-1[Gi-2+ Pi-2Ci-2] =Gi + PiGi-1 + PiPi-1Gi-2 + PiPi-1Pi-2Ci-2 Ci+1 = Gi + PiGi-1 + PiPi-1Gi-2+…..+PiPi-1….P1G0 + PiPi-1…P0C0 One will notice one important thing: to calculate thei+1th, carry you only need C0.You don‟t need the chain now. As soon as you apply the value of X,Y and C0 the sum is obtained in 3 gate delay (instead of n gate delay) as below: o One gate delay to calculate ALL Pi and Gi o One gate delay for AND logic (ex PiGi-1) o One more gate delay to do the OR logic (ex: Gi+PiGi+…+…+) Hence, in 3 gate delay we get the carry. o For sum we need to do one final XOR. Hence One more XOR for sum Hence, the sum is obtained in four gate delays.  A 4-bit carry-lookahead adder circuit is given in the following figure: The carry C1, C2, C3, C4 can be represented in terms of G and P as below: C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1(G0+ P0C0) = G1+ P1G0 + P1P0C0 C3 = G2+ P2C2 = G2+ P2G1 + P2P1G0 + P2P1P0C0 C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 The above circuit is called a carry-lookahead adder. Carry-lookahead circuit calculates C1,C2,C3,C4 using Pi and Gi. This circuit uses 3 gate delays for all carry and 4 gate delays for sum. In comparison the 4 –bit ripple carry adder uses 7 gate delays for S3 and 8 gate delays for C4.  Multiple 4 bit carry look ahead adder can be used to implement n-bit address.  For example: Eight 4-bit adders can be connected together to form a 32-bit adder. In this case sum S31 and carry C32 are available after 63 and 64 gate delays respectively. Higher – level Generate and Propagate Function The figure below shows the 16-bit carry –look ahead adder built using 4-bit adders. UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 6 For the above figure 6.5, we have P0 I = P3P2P1P0 G0 I = G3+ P3G2 + P3P2G1 + P3P2P1G0 The final carry generated is C16.This can be represented as: C16 = G3 I + P3 IG2 I + P3 IP2 IG1 I + P3 IP2 IP1 IG0 I+P3 IP2 IP1 IP0 IC0 Now let‟s see the delay  The sum S15 is available after 8 gate delays. The C16 carry is available after 5 gate delays. If a 32-bit adder is created by cascading two 16-bit address, in such a configuration  The sum S31 is available in 10 gate delays.  The carry C31 is available in 9 gate delays. However, if the same 32-bit adder is created by cascading eight 4-bit lookahead adders, then the gate delays will be:  The sum S31 is available in 18 gate delays  The carry C31 is available in 17 gate delays 6.3 Multiplication of Positive Numbers:  When two “n” bits numbers are multiplied by hand it is done as below. For ex:  The above method of multiplication can be implemented as shown: UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 7 The square box represents a single cell that implements partial product for one bit as shown: o Each row i, where 0 ≤ i ≤ 3 adds the multiplicand to the incoming partial product, PPi to generate the outgoing partial product, PP(i+1), if qi=1. However, if qi=0, PPi is passed vertically downwards unchanged. o Note: The worst case signal propagation delay path is from the upper right corner of the array to the higher order product bit at the bottom left corner of array. o The path has a total of 6(n-1)-1 gate delays including initial AND gate delay in all cells for n X n array.  The other method to perform multiplication is to use the adder circuitry in the ALU for a number of sequential steps. The figure below shows the sequential circuit binary multiplier: Now, let‟s take the example as before: M = 1101, A = 0000, Q = 1011, C = 0 As per above circuit diagram the following has to be done Step 1: Add M and A (only if LSB of Q i.e. q0 = 1). Step 2: Store the result in A and carry bit(if any in C) Step 3: Shift by 1 bit the pattern “C A Q” Round 1 Step 1: Add M and A (only if q0=1. Since q0=1 we can add M and A) . Step 2: Store the result in A and carry = 0 in C Step 3: Shift right by 1 bit the C A Q value. New values in C A and Q after shift right by 1 bit is UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 10 Booth algorithm can be visualized using following steps: Let Multiplicand = 0101101 Multiplier = 0011110 Step 1: Put a 0 at the end of multiplier 00111100  extra 0 at the end Step 2: Start from right side and take 2 bits at a time. Look at the table and pick the appropriate value. Ex: For above multiplier (0011110), the new multiplier is calculated as: So, the new multiplier is Step 3: Now, perform the multiplication keeping in mind that:  If -1 is the multiplier then partial sum will be 2‟s complement of multiplicand  If multiplier is 0, partial sum will be all 0‟s  If multiplier is 1, then partial sum will be the multiplicand. Calculations are done as shown in below example: In the above example we notice that when “-1” was encountered the partial sum was 2‟s complement of multiplicand. Example: Another example here the multiplier is negative. 01101 (+13) 11010 (-6) Solution: Step 1: Put a 0 at the end of multiplier. So the multiplier is 110100. Step 2: Start from right side, pick 2 bits at a time and based on table generate a new multiplier calculated as below: Step 3: Apply below logic  If multiplier bit is 0, then partial sum is all 0‟s  If multiplier bit is +1 then partial sum is same as multiplicand  If multiplier bit is -1 then partial sum is 2‟s complement of multiplicand UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 11 Worst case, ordinary, Best Case multiplier A multiplier is a worst case multiplier if it has alternate 0‟s and 1‟s.The resulting multiplier after applying the table will contain alternate +1 and -1 as below. A multiplier with a bunch of 0‟s and 1‟s is a best case/good multiplier. An ordinary multiplier has random bunch of 0‟s and/or 1‟s. 6.5 Fast Multiplication Bit-Pair Recoding of Multipliers • Group the booth recoded multiplier bits in pairs, and it can be observed, that, the pair (+1, -1) is same to the pair (0, +1), i.e., Instead of adding -1 x M at shift position i with +1 x M at i+1, it can be added with +1 x M at position i. • Bit-pair recoding halves the maximum number of summands (versions of the multiplicand). UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 12 Example: The above addition can be done using table (b) as below: Carry-Save Addition (CSA) of Summands Carry save addition speeds up the addition process. In CSA, instead of letting the carries ripple along the rows, they can be saved and introduced into next row, at correct weighted positions. The full adder is input with three partial bit products in the first row.  Multiplication requires the addition of several summands.  CSA speeds up the addition process.  Consider the array for 4x4 multiplication shown in fig(1).  First row consisting of just the AND gates that implement the bit products m3q0,m2q0,m1q0 and m0q0 . UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 15  There are two ways to perform the division. (a) Restoring Division (b) Non Restoring Division Let‟s look at both the methods below. Restoring Division:  Register M is loaded with n-bit divisor  Register Q is loaded with n-bit dividend  Register A is initially set to 0  The final quotient will be stored in n bit Q register.  The final reminder will be stored in n-bit “A” register. The figure right side, shows the division circuit. The algorithm for division is as below (for restoring division) Do the following “n” times:  Shift A and Q left one binary position  Subtract M from A and place the answer back in A.  If the sign of A is 1, set q0 to 0 and add M back to A (that is restore A) otherwise set q0 to 1. Let‟s take an example and see the steps: Initially A = 00000 Q= 1000 M = 00011 We canshow A and Q both together as: 000001000 A Q Round 1: Step 1: Shift A and Q left one binary position Step 2: Subtract M from A (or rather add 2‟s complement of M to A) M = 00011. 2‟s Complement of M = 11101 Adding‟s 2‟s complement of M to A gives:  New A Step 3: If sign of A is 1 (Yes MSB of A is 1, so set q0 to 0). So Q looks as: Add M to A so that we can restore back A i.e. add 00011 to 11110 At this point: UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 16 Round 2: Step 1: Shift A and Q left one binary position so new A Q is: Step 2: Subtract M from A (i.e. add 2‟s complement of M to A)  New A Step 3: If sign of A is 1(yes MSB of A is 1) so set q0 to 0, hence Add M to A so that we can restore back A i.e. add 00011 to 11111 At this point: Round 3: Step 1: Shift A and Q left by one position. So new value of A and Q are Step 2: Subtract M from A (i.e. add 2‟s complement of M to A) Step 3: If sign of A is 0 (yes MSB of A is 0) then just set q0 to 1. Round 4: Step 1: Shift A and Q left by one position. So new value of A and Q are Step 2: Subtract M from A (i.e. add 2‟s complement of M to A)  New A Step 3: If sign of A is 1 (which is true), then Add M to A(i.e. restore A) and set q0 to 0. Q = 0 0 1 0 Hence after 4 rounds we have the, remainder in A i.e. 00010 and Quotient is Q i.e. 0010 UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 17 The above steps can be written as below: Non-restoring Division: Non-restoring division algorithm does the following Step 1: Do the following “n” times. o If the sign of A is 0, shift A and Q left one bit position and subtract M from A; otherwise, shift A and Q left and add M to A. o Now, if the sign of A is 0, set q0 to 1; otherwise, set q0 to 0. Step 2: If the sign of A is 1, add M to A. Example: Let‟s take the same example Solution: Initially A=00000 M= 00011 Q =1000 Let us do the Step 1 “n” number of times (“n” here is 4 so 4 rounds are done for step 1) Round 1: Sign of A is 0 so shift AQ left by 1 position and subtract M from A. A-M gives the following:  New A Sign of A is 1, so set q0 to 0. Hence, Round 2: Sign of A is 1 Shift AQ left by 1 bit and add M to A. A+M gives the following: UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 20 o 1 bit for sign (+ or-) (S) IEEE floating point for 32-bit (single precision) is as shown below: The value that above figure represents is a binary number in the range = +1.M x 2E‟-127 Ex: Suppose that I want to store 1.001010…0 x 2 -87 in a 32 bit word then I do the following. Solution: S=0 (sign bit is 0 because it is a +ve number) E‟ = E + 127 (or E=E‟ -127) E‟ = -87 + 127 = 40 = 00101000 M = 001010…0 (from the problem itself i.e. number after decimal point) So, 1.001010…0 x 2-87 is stored in 32 bits. 0 00101000 001010……..0 Ex: Suppose I want to store 1.111100….0 x 2-126 Solution: S = 0 (+ve number so sign bit is 0) E‟ = E + 127 = -126 + 127 = 1 = 00000001 (there are 8 bits for E‟) M = 111100….0 (all numbers after decimal point). 0 00000001 111100…0 Ex: Suppose the 32 bit memory contains the following, then what is the value. 0 00000011 011010…0 Solution: S = 0 (+ve number) E‟ = 0000011 = 3 So, E = E‟ – 127 = 3 – 127 = -124 M = 011010 Hence, the memory is storing 1.011010 x 2-124 Note: In all the above examples the number “1” is added implicitly to the number. This is not stored anywhere. For a number in normalized form, the number on the left of decimal point is always 1. Double Precision: The 32 bit representation described above has a range of 2-126 to 2+127 i.e. decimal number in the range of 10-38 to 10+38 can be stored at the maximum. If we want to store higher range between 2-1022 to 2+1023 (i.e. in decimal numbers between 10-308 to 10308) then the length of the word has to be 64 bits with the following split: o Sign bit = 1 bit o Exponent = 11 bits (Excess -1023 component) o Mantissa = 52 bits UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 21 Value represented = ± 1.𝑀 × 2𝐸 ′−1023 This representation in 64-bits is called a double precision. Special Values: E‟ and M can take special values i.e. 0 and 255. The combination of E‟ and M values of 0 and 255 the combination of E‟ and M values 0 and 255 have special meaning as below: E‟ M Meaning 0 0 Number 0 255 0 ∞ (For example x/0 results in ∞ 0 ≠ 0 Denormal numbers i.e. very small numbers 0…M x 2 -126 255 ≠ 0 Not a number(NAN) ex 0/0 results in this value Exceptions:  Arithmetic operations on two floating point numbers can result in a number whose exponent is less than -126 ex: 1.0110 x 2-3500 This cannot fit in a 32-bit floating point representation as it can hold only upto 1.M x 12-126.This situation is called “underflow” where a number is too small to hold a 32-bit. Arithmetic operation could result in numbers which might result in floating point numbers more than +127. This situation is called an “overflow” where a number is too big to hold in 32 bits.  Processor has flag (exception flags) to indicate this scenario. o Underflow: bit set when underflow occurs o Overflow: bit set when overflow occurs o Divide by zero: bit set when a number is divided by zero o Inexact: If a number is rounded off to fit in a normal format o Invalid: If we do a 0/0 or −1 is attempted then invalid flag is set.  When the above flags are set there are two options (a) Processor triggers an interrupt so that the situation is handled. (b) No interrupt is triggered, however the application checks for the flags to decide and take next step. 6.7.2 Arithmetic Operations on Floating Point Numbers Floating point numbers can undergo various operations like addition, subtraction, multiplication and division. This section describes the rules Note: Overflow and underflow are not considered in this section. Note: If the exponents of both operand differ they have to be first brought to common operand and then calculations are done. Ex. In decimal calculation if we want to do 2.94 x 102 + 4.31 x 104, we need to first bring them to common exponent i.e. 0.0294 x 104 + 4.31 x 104 . Floating point arithmetic also expects the same. Addition/Subtraction 1. Choose the number with the smaller exponent and shift its mantissa right a number of steps equal to the difference in exponents. 2. Set the exponent of result equal to the larger exponent. 3. Perform addition/subtraction on the mantissas and determine the sign of the result. 4. Normalize the result value if necessary Multiplication Rule: 1. Add the exponents and subtract 127. 2. Multiply the mantissas and determine the sign of result. 3. Normalize the result value if necessary Division rule: 1. Subtract the exponents and add 127 2. Divide the mantissa and determine the sign of the result. 3. Normalize the result value if necessary. UNIT VI – Arithmetic Faculty in Charge: RK, AMV Dept. of ISE, RNSIT 22 6.7.3 Guard Bits and Truncation:  During arithmetic operations on floating point numbers, the mantissa result could be bigger than the 24 bits (including implicit 1). These extra bits are guard bits. These are retained during intermediate calculations.  However final result needs to fit in 24 bits for mantissa. Here these guard bits need to be removed. The process of removing the guard bits is called Truncation.  These are different ways of truncating as shown below: (a) Chopping:  Remove the guard bits and retain the bits that need to be retained. Ex: Let the floating point number be : 0.b-1b-2b-3b-4b-5b-6 let‟s assume we are supposed to retain only 3 bits after decimal point. Then as per chopping rule simply drop b-4,b-5,b-6. Hence final result is 0.b-1b-2b-3.  So all numbers between 0.b-1 b-2 b-3 000 to 0.b-1b-2b-3111 are truncated to 0.b-1b-2b-3  The error in final answer ranges from 0 to 0.000111.  Ex: If 0.101000 is truncated to 0.101 then error is 0.  Ex: If 0.101111 is truncated to 0.101 then error is 0.000111. (b) Von Neumann Rounding:  If bits to be dropped are all 0‟s then simply drop them.  If any of the bits to be removed is 1 then the last retained bit is set to 1.  Ex: If 0.100000 is rounded by Von Neumann rounding, it is rounded to 0.100 (i.e. b-4,b-5,b-6 are simply dropped).  Ex: If 0.100010 is rounded by Von Neumann rounding, it is rounded to 0.101 (last retained bit is set to 1 because one of the dropped bits(b-5) is 1 hence b-3 is set to 1). (c) Rounding procedure  The third procedure is called rounding procedure. The rule is as below.  A 1 is added to LSB position of the bits to be retained if there is a 1 in the MSB position of the bits to be removed.(ex b-4).  Ex: if the number is 0.b-1 b-2 b-3 100… then it is rounded by adding 0.001 to it i.e.: 0. b-1 b-2 b-3 +0.001  Ex: If number is 0.b-1b-2b-3 000. Then it is rounded by dropping the 000‟s to b-1b-2b-3. (d) Round to nearest even number.  The aim is to round the retained bits (example: b-1b-2b-3) to nearest even number.  Example: If the LSB of retained bit is 0(example: b-1 b-2 b-3) then it is retained as it is even if MSB of dropped bit is 1.  (Example: b-1b-20100 -> b-1b-20 i.e. b-3 is retained as 0 as is).  Ex If the LSB of retained bit is 1(example: b-1b-21) and if dropped bits MSB is 1(example: b-1b- 21100) then make retained bits to nearest even number (example: b-1b-21100 + 0.001) by adding 0.001, the number b-1b-21 becomes an even number. (e) Sticky Bit During intermediate calculation, 3rdbit of all the guard/dropping bits are retained .The first two bits are the two MSB bits of mantissa and the third bit is a logical OR of all mantissa bits. This bit is called sticky bit. 6.7.4 Implementing Floating Point Operations The figure below (Figure 6.26) shows an addition-subtraction unit that performs the addition-subtraction of floating point number. From section 6.7.2 we know that addition/subtraction has 4 rules: Rule 1: Choose the number with smaller exponent and shift its mantissa right a number of steps equal to the difference of exponent. We know each floating point number has 3 components sign, exponent and mantissa. Let A and B be the two floating point numbers (32-bit operands) as below: