Lab 9: Designing Muller C-Element with Static CMOS Tech and Two-Phase Handshake - Prof. Ja, Lab Reports of Digital Electronics

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Laboratory Nine

Design of a Muller C-Element

References

Mentor On-Line Help Manual Mentor Tutorials posted on the ECE 4500/5950 Class Web Page

Objectives

1. Design an asynchronous circuit for self-timed handshake signaling using static CMOS technology.
2. Simulate a two-phase handshake signal protocol using a Muller C-element.

Specifications

You will develop a concise layout for the static CMOS implementation of a Muller C-element. A functional block diagram of the module is depicted in Figure 10.41(a) on Page 527 of your Text. Work with the 6-transistor asynchronous CMOS SR latch cell that you have developed in Lab 6.

Inputs are notA, B, and CLR (active-high reset), and output is F. The Function Table is given in Figure 10.40(b) but it exhibits input A, instead, and does not include the reset input CLR.

Use the simple system block diagram in Figure 10.42 to simulate a two-phase handshake protocol. Signal Ack should also become an input to the Sender logic block. You need to insert a 5ns delay between signals Ack and Data Ready in the Sender logic and between Req and Ack in the Receiver logic, respectively. in order to verify the correct operation of the handshake protocol.

The terminal configuration of the layout should allow access to all signals from both top and bottom of the module. The power lines should be on first-layer metal rails that pass completely through the module in a horizontal direction. Be as generous as you can with the widths of the power lines so that their current-carrying capacities will be reasonably high. The minimum feature sizes for L and W are 1.2μm and 2.0μm, respectively.

Tasks:

1. Capture the schematic diagram of your counter using Design Architect. Name your file like xxx_lab.
2. Design a suitable functional simulation for the circuit using Eldo and Xelga. Verify the specified functions for the circuit on the basis of your simulation results.
3. Use Eldo and Xelga for transient analysis. From transient analysis, obtain tPHL, tPLH, and tP.
4. Create a layout for the circuit.
5. Perform parasitic extraction.

Lab Report (hard copy) should include: a) Discussion of your design (a transistor-level schematic diagram is included). b) Printout of the schematic diagram. c) Printout of the layout. d) Printouts of the functional simulation using Eldo and Xelga. e) Printouts of the transient simulations. f) Final specs of your circuit (logic levels VOL, and VOH, delay times tPLH and tPHL, the average delay tP , and the size of the actual layout area).

Bonus credit: the two best designs (the product of the size of the layout area and the propagation delays is at minimum) will be given up to 20% bonus credit at the discretion of the course instructor.