Test Paper - Electronic Devices and Circuits - II - Mumbai University - Electronics and Telecommunication Engineering - 4th Sem. - 2009, Study notes of Analysis and Design of Digital Integrated Circuits

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Con. 2580-09.

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(REVISED COURSE).

(3 Hours) [Total^ Marks:^100

N.S.: (1) Question Nos. 1 and 2 are compulsory. (2) Attempt three questions from the remaining five questions. (3) Assume suitable data if necessary.

1. (a) Draw the low frequency model of a JFET and obtain expressiQnsfor the'voltage 10 gain, input impedance, output imped~nce in CS Amplifier.. (b) Show the effect of low frequency and high frequency on coupling and bypass 1. capacitors.

2:' (a) For a 'cascaded amplifier, show that the overall lower 3 dp frequency,

t rx:-

tT = (^) I 1/ and fHT= fH 'J2/n -1 with n stages..

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(b) A differential amplifier has a differential gain 50 dPs, CMRR = 75 dPs.

Vs1 = 15 mv. Vs2 = 10 mv. Find error voltage and % error in the output voltage.

10

10

3. (a) The followingcircuit has the parameters. Rc = 4 kQ. R' = 40 kQ, Rs = 10 kQ, 12 hie = 1.1 kQ. hfe= 50, hre = hoe = O.. Find AVf' Rif ' Rof ' Rit', R'of

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(b) Explain the various feedback topologies. 8

4. (a) Derive an expression for the frequency of oscillation of a transistorized RC 12 phase-shift oscillator.. (b) A class A transformer coupled circuit is to deliver a maximum power of 6W 8 to 4 Q load. Vcc = 25 V. Vmin = O. Find, N (i) Transformer turn ratio (n-) = N~ (ii) Peak collector current 1m' (iii) Q (lc' VCE). (iv) Conversion efficiency.

5. (a) Explain the operation ofa Schmitt Trigger with a neat sketch. 10

(b) Design a phase shift oscillator using FET having a gm = 5000 k U. rd = 40kQ, 10 and a FB circuit of R = 10 kQ. Frequency of oscillation is 1 KHz.

[ TURN OVER

Con. 2580-VR-3825-09.

6. (a)

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For the followingcircuit, Vcc = 12 V. RL =4.7 kQ, RE = 1 kQ, R1 = 15 kQ, R2 = 2.2 kQ, Rs = 600 Q. hfe= 100, hie.= 1K. Find, -

. (i) Calculate mid frequency voltage gain ~oS and ~~I

(ii) Calculate the size of bypass capacitor if fL = 50 Hz. (iii) Calculate the size of coupling capacitor if fL = 50 Hz.

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(b) For the amplifier shown below, it is desired to haul tower 3dr3 frequency of not more than 20 Hz. If hie = 1.1 kQ. hfe = 120, Rs = 100' Q. What is the value of Cc required? Assume Ce = Cc' (b) Repeat part (a) if Ce = 50 Cc

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Con. 2580-VR-3825-09.^3

7. (a) The following circuit has the parameters-

hlb = 50 0, hfb= - 0.99, hrb= hOb= 0 hie = 5000, h'e = - 100, hre = 1 and hoc = O.

(i) Find the overall voltage gain = Va Vs

(ii) Find the overall current gain = -!1-. IS

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(b) For the power amplifier shown below, lca = 20 mA, RL = 200 Vcc= 24 V., Re = 200 O. Find (i) max. undistorted output voltage. (ii) max. peak current through the transistor collector. (iii) max. undistorted ac power output.

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