VHDL Lab: Designing Digital Circuits using Xilinx and VHDL - Prof. Samuel Lee, Lab Reports of Digital Systems Design

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Xilinx VHDL Lab

Create a new project titled “VHDL_LAB2” and create each of these circuits as a new VHDL module within the project. Also create individual test bench waveforms for each module. For each problem submit copies of the VHDL code and simulated waveforms.

1. Using truth tables and k-maps design a 3 input majority rules circuit. If 2 or more inputs are low then the output is low. If two or more inputs are high then the output is high. Implement this circuit in VHDL with the three inputs named A, B, and C and the output named Z. Simulate all possible input combinations (8 steps).
2. Design VHDL code for a 2-to-1 line multiplexer (MUX) that has two inputs, A and B, and an asserted high enable, E. The select input, S, selects the A input when asserted low and the B input when high. When not enabled the multiplexer output, M_OUT is low. Provide a simulation that first drives all data inputs high with E low (one simulation timing step). Next, assert E high and S low, then make the A low one step and then high with the B input held low (two steps). Next, with E high and S high, make B input low and then high with the A input held low (two steps).
3. Design VHDL code for a 2-to-4 line decoder that has 2 inputs, A and B, an asserted high enable E, and 4 outputs Y0, Y1, Y2, Y3. When not enabled all outputs should be low. Provide a simulation that steps through all combinations of A and B with E low (four steps). Then repeat all combinations of A and B with E high (four steps).
4. For the “decode24” VHDL Module created above, select it in Sources for “Implementation” and then under Processes
   Design Utilities, run “Create Schematic Symbol”. After the schematic symbol is successfully created, add a new source to your project and select “Schematic” (not “VHDL Module”). Give your schematic a useful name (e.g. “lab2schematic”). You should now see a blank schematic titled “lab2schematic”. Now in Sources there should be a tab, “Symbols”, where you can select IC symbols to add to the circuit such as AND and OR gates. In “Categories” and underneath “<--All Symbols-->” there should be a category that looks something like: “<C:/xilinx/VHDL_Lab2/>” (depending on where you saved your project). These are the schematic symbols that you have created for the modules in your project. Utilizing the decoder you just created along with a built in “or2” gate, create an XOR gate. Select “decode24” and place it on the schematic. Then add I/O Markers (using the “Add I/O Marker” toolbar button) to the inputs. Provide meaningful names to these I/O Markers by double clicking on the markers (you can just name them “A”, “B”, and “E”). Add an “or2” gate and connect the appropriate outputs from “decode24” using the “Add Wire” toolbar button. Then add an I/O Marker to the output of the “or2” gate and rename it. Finally, create a TestBench Waveform for your schematic that you have created

and test all the combinations of inputs. Also note that you can create a schematic symbol or generate VHDL code for this new circuit that you have created. These can then be used to create other (more complex) circuits.