Many Processors One Chip  -  Computer Systems Architecture - Lecture Slides, Slides for Computer Architecture and Organization. Alagappa University
jutt
jutt

Many Processors One Chip - Computer Systems Architecture - Lecture Slides, Slides for Computer Architecture and Organization. Alagappa University

PDF (266 KB)
22 pages
1000+Number of visits
Description
Some concept of Computer Systems Architecture are Acyclic Graph, Advanced Micro Devices, Basic Grid Architecture, Control Flow Prediction, Desktop Processor Architecture, Message-Driven Processor. Main points of this lec...
20 points
Download points needed to download
this document
Download the document
Preview3 pages / 22
This is only a preview
3 shown on 22 pages
Download the document
This is only a preview
3 shown on 22 pages
Download the document
This is only a preview
3 shown on 22 pages
Download the document
This is only a preview
3 shown on 22 pages
Download the document

MPOC “Many Processors, One Chip”

1 Docsity.com

AGENDA

• Introduction • Project Team • Design Aims • 4-stage Pipeline • Memory • Result

2 Docsity.com

INTRODUCTION

• Project at Hewlett Packard's Palo Alto Research Lab

• Between years 1998 and 2001 • Stands for “Many processors, one chip”

3 Docsity.com

INTRODUCTION

• A single-chip community of identical high-speed RISC processors surrounding a large common storage area

• Each processor has its own clock, cache and program counter

• In order to reach min. power consumption, each processor is to be small and simple, but run very fast using that min. power requirements.

4 Docsity.com

PROJECT TEAM • Stuart Siu, circuit design • Stephen Richardson, logic design and project management • Gary Vondran, Project Lead and logic design • Paul Keltcher, processor simulation, application development • Shankar Venkataraman, OS and application development • Krishnan Venkitakrishnan, logic design and bus architecture • Joseph Ku, circuit design • Manohar Prabhu and Ayodele Embry, interns

5 Docsity.com

DESIGN AIMS

1) novel funding for microprocessor research; 2) introducing multiprocessing to the embedded

market; 3) trading design complexity for coarse grain

parallelism; 4) a novel 4-stage microprocessor pipeline; 5) using co-resident on-chip DRAM to supply chip

multiprocessor memory needs.

6 Docsity.com

4-STAGE PIPELINE

• F-stage to fetch the instruction from the instruction cache,

• D-stage to decode the instruction, • E-stage to calculate arithmetic results and/or a

memory address, • M-stage during which the processor can access the

data cache; • W-stage during which the processor writes results

back to its register file.

7 Docsity.com

4-STAGE PIPELINE

• F-stage to fetch the instruction from the instruction cache,

• D-stage to decode the instruction, • E-stage to calculate arithmetic results and/or a

memory address, • M-stage during which the processor can access the

data cache; • W-stage during which the processor writes results

back to its register file.

8 Docsity.com

4-STAGE PIPELINE

Reasons for eliminating M-stage: • small first level caches can be accessed in a

single cycle • simple base-plus-offset addressing scheme of

the MIPS instruction set allowed addresses to be calculated in the second half of the D stage

9 Docsity.com

4-STAGE PIPELINE / LOAD & STORE

10 Docsity.com

4-STAGE PIPELINE / LOAD & STORE

• The hit or miss signal for a data cache access does not appear until late in the E stage of the pipeline.

11 Docsity.com

4-STAGE PIPELINE / LOAD & STORE

• LOAD => The data has already been fetched from the cache, but the miss signal can simultaneously halt the pipeline and prevent the incorrect data from being written to the register until the correct data arrives

12 Docsity.com

4-STAGE PIPELINE / LOAD & STORE

• STORE => The miss signal arrives in time to prevent incorrect data from going into the cache until the tags can be updated, dirty data can be written out to memory if necessary, and the pipeline can be restarted.

13 Docsity.com

4-STAGE PIPELINE / LOAD & STORE

• STORE THEN LOAD => Single bubble!

14 Docsity.com

4-STAGE PIPELINE / LOAD & STORE

• ALU THEN LOAD => Single bubble!

15 Docsity.com

4-STAGE PIPELINE / LOAD & STORE

• LOAD THEN A DEPENDENT INST => NO bubble!

16 Docsity.com

4-STAGE PIPELINE / BRANCH

• The instruction following a branch is always executed, regardless of the direction eventually taken by a branch.

• This extra instruction allows the pipeline to calculate the target of the branch, so that it can speculatively fetch the target in the following cycle.

17 Docsity.com

4-STAGE PIPELINE / BRANCH

• NO penalty for taken branch:

• 1 cycle penalty for non-taken branch:

18 Docsity.com

4-STAGE PIPELINE / BRANCH

19 Docsity.com

MEMORY

• In MPOC’s original plan, 1MB to 4MB of DRAM is placed on the same silicon die with the four processors.

20 Docsity.com

MEMORY

Ways of managing local memory: • Cache organized as set of data lines • Unified physical address space that includes

both local and remote memory

21 Docsity.com

RESULT

• Final status of the design:

22 Docsity.com

no comments were posted
This is only a preview
3 shown on 22 pages
Download the document