Download Memory Hierarchy: Understanding Cache, SRAM, and DRAM - Prof. Kirk Cameron and more Study notes Computer Architecture and Organization in PDF only on Docsity! 1 The memory gap 1980: no cache in µproc; 1995 2-level cache on Alpha 21164 µproc • DRAM: – value is stored as a charge on capacitor (must be refreshed,RAS/CAS) – very small but slower than SRAM (factor of 5 to 10) • SRAM: – value is stored on a pair of inverting gates (e.g. D-Latch) – very fast but takes up more space than DRAM (4 to 6 transistors) Memory Technology Review W ord li ne Pass transistor Capacitor Bit line General Principles • Locality – Temporal Locality: referenced again soon – Spatial Locality: nearby items referenced soon • Locality + smaller mem is faster = memory hierarchy – Levels: each smaller, faster, more expensive/byte than level below – Inclusive: data found in top also found in the bottom • Definitions – Upper is closer to processor – Block : minimum unit that present or not in upper level – Address = Block frame address + block offset address – Hit time: time to access upper level, including hit determination Why does code have locality? Locality • Temporal locality – Recently used item is likely to be re-used in near future • Spatial locality – Addresses close together physically tend to be referenced close together in time 90/10 Locality Rule: Code executes 90% of its instructions in 10% of its code. The memory hierarchy SRAM DRAM Users want large, fast memories cheap! (conflict) cost/capacityspeed/capacity Lower power, faster Refreshing, less expensive The memory hierarchy CPU Level n Level 2 Level 1 Levels in the memory hierarchy Increasing distance from the CPU in access time Size of the memory at each level 2 Who’s in control? Storage Memory Cache Registers cost size hardware compiler OS OS/user Four Questions for Memory Hierarchy Designers • Q1: Where can a block be placed in the upper level? (Block placement) • Q2: How is a block found if it is in the upper level? (Block identification) • Q3: Which block should be replaced on a miss? (Block replacement) • Q4: What happens on a write? (Write strategy) Q1: Where can a block be placed in the upper level? Q2: How Is a Block Found If It Is in the Upper Level? • Tag on each block – No need to check index or block offset • Increasing associativity shrinks index, expands tag FA: No index DM: Large index IndexTag Block Offset Block Frame Address Find block in set Select set Block address compared to block frame address (tag) for all frames in cache in parallel Given a block address, it can only be found in the set specified in index. All tags in index set must be compared to block address (in parallel) to f ind a hit . Q2: How Is a Block Found If It Is in the Upper Level? IndexTag Block Offset Block Frame Address ta g ta g index ta g ta g index ta g ta g index ta g ta g index ta g ta g ta g ta g ta g ta g ta g ta g in de x in de x in de x in de x in de x in de x in de x in de x Given a block address, it can only be found in the set specified in index. All tags in index set must be compared to block address (in parallel) to f ind a hit . FA: No index DM: Large index B lo ck a dd re ss ta g ta g ta g ta g ta g ta g ta g ta g Q3: Which Block Should be Replaced on a Miss? • Easy for Direct Mapped • Set Associative or Fully Associative: – Random (for large associativities, simple) – LRU (for smaller associativities, more complex) – FIFO (approximate LRU) Alpha 21264: Data cache misses per 1000 instructions
