Practice Exam Solutions - Introduction To Digital System Design | ECE 27000, Exams of Digital Systems Design

Download Practice Exam Solutions - Introduction To Digital System Design | ECE 27000 and more Exams Digital Systems Design in PDF only on Docsity! ECE 270 Outcome 1 Assessment - 1 - Practice Exam / Solution ______________________________________________________________________________ © 2009 by D. G. Meyer / Purdue University – may not be copied or reproduced, in any form or by any means. OUTCOME #1: “an ability to analyze static and dynamic behavior of digital circuit.” Multiple Choice – select the single most appropriate response for each question. Note that “none of the above” MAY be a VALID ANSWER. 1. For most CMOS logic families, the maximum acceptable VIL is: (A) 10% of the power supply voltage (B) 30% of the power supply voltage (C) 50% of the power supply voltage (D) 70% of the power supply voltage (E) 90% of the power supply voltage 2. The nominal (minimum) case for the outputs of logic family “A” to be able to successfully drive the inputs of logic family “B” is: (A) fanoutA→B ≤ 1 and DCNMA→B < 0 (B) fanoutA→B ≤ 0 and DCNMA→B < 1 (C) fanoutA→B ≥ 1 and DCNMA→B > 0 (D) fanoutA→B ≥ 0 and DCNMA→B > 1 (E) none of the above 3. If a CMOS gate input voltage is 50% of its Vcc (power supply) voltage, then: (A) the logic gate will dissipate less power than it would if the input was 1% of its power supply voltage (B) the logic gate will dissipate less power than it would if the input was 99% of its power supply voltage (C) the logic gate will dissipate more power than it would if the input was either 1% or 99% of its power supply voltage (D) the logic gate will dissipate no power (E) none of the above 4. A microcontroller designed to operate over a power supply range of 2 V to 4 V and a clock frequency range of 0 to 60 MHz dissipates a maximum of 320 mW. If the supply voltage used is 3 V and the clock frequency is 40 MHz, the power dissipation of the microcontroller will be reduced to: (A) 60 mW (B) 120 mW (C) 160 mW (D) 180 mW (E) none of the above Place answers on the supplied BUBBLE SHEET only – nothing written here will be graded. Please REATTACH your completed bubble sheet to this document and turn BOTH in TOGETHER. ECE 270 Outcome 1 Assessment - 2 - Solution © 2009 by D. G. Meyer ______________________________________________________________________________ © 2009 by D. G. Meyer / Purdue University – may not be copied or reproduced, in any form or by any means. The following table applies to questions 5 through 8: Table 1. DC Characteristics of a Hypothetical Logic Family. VCC = 5 V VOH = 3.50 V VOL = 0.50 V VIH = 2.50 V VIL = 1.00 V VTH = (VOH – VOL)/2 IOH = −5.0 mA IOL = 10 mA IIH = 500 µA IIL = −2.0 mA 5. The DC noise margin for this logic family is: (A) 0.50 V (B) 1.00 V (C) 1.50 V (D) 2.00 V (E) none of the above 6. The practical fanout for this logic family is: (A) 1 (B) 2 (C) 5 (D) 10 (E) none of the above 7. When interfacing an LED that has a forward voltage of 1.5 V to this logic family in a current sourcing configuration, maximum brightness will be achieved (within the rated specifications) using a current limiting resistor of the value: (A) 200 Ω (B) 300 Ω (C) 400 Ω (D) 500 Ω (E) none of the above 8. When interfacing an LED that has a forward voltage of 1.5 V to this logic family in a current sinking configuration, maximum brightness will be achieved (within the rated specifications) using a current limiting resistor of the value: (A) 200 Ω (B) 300 Ω (C) 400 Ω (D) 500 Ω (E) none of the above ECE 270 Outcome 1 Assessment - 5 - Solution © 2009 by D. G. Meyer ______________________________________________________________________________ © 2009 by D. G. Meyer / Purdue University – may not be copied or reproduced, in any form or by any means. The following circuit applies to questions 15 through 17: 15. This circuit implements the following type of logic gate: (A) two-input OR (B) two-input AND (C) two-input NOR (D) two-input NAND (E) none of the above 16. If the “on” resistance of the MOSFET labeled “QP” is 200 Ω and the “on” resistance of the MOSFET labeled “QN” is 100 Ω, then if 10 mA of current is sourced in the high state, VOH will be: (A) 1 V (B) 2 V (C) 3 V (D) 4 V (E) none of the above 17. If the “on” resistance of the MOSFET labeled “QP” is 200 Ω and the “on” resistance of the MOSFET labeled “QN” is 100 Ω, then if 10 mA of current is sunk in the low state, VOL will be: (A) 1 V (B) 2 V (C) 3 V (D) 4 V (E) none of the above 5 V GND A A B B F QP QN “on” resistance = 200 Ω “on” resistance = 100 Ω ECE 270 Outcome 1 Assessment - 6 - Solution © 2009 by D. G. Meyer ______________________________________________________________________________ © 2009 by D. G. Meyer / Purdue University – may not be copied or reproduced, in any form or by any means. The following figure applies to questions 18 through 19 (assume each horizontal division is 1 nanosecond): 18. Based on the definition provided in the course text, the fall time (tTHL) for the inverter is approximately: (A) 1.0 ns (B) 1.5 ns (C) 2.0 ns (D) 3.0 ns (E) none of the above 19. The rise propagation delay (tPLH) for the inverter is approximately: (A) 1.0 ns (B) 1.5 ns (C) 2.0 ns (D) 3.0 ns (E) none of the above X Y X Y 1 ns ECE 270 Outcome 1 Assessment - 7 - Solution © 2009 by D. G. Meyer ______________________________________________________________________________ © 2009 by D. G. Meyer / Purdue University – may not be copied or reproduced, in any form or by any means. 20. A “floating” (unconnected) gate input will most likely cause the gate’s output to: (A) always be high (B) always be low (C) be one-half (50%) of the supply voltage (D) be unpredictable (E) none of the above 21. A CMOS circuit only consumes a significant amount of power: (A) when warming up (B) when cooling off (C) during output transitions (D) during input transitions (E) none of the above 22. The primary purpose of decoupling capacitors is to: (A) provide an instantaneous source of current during output transitions (B) increase the output current sourcing/sinking capability (C) prevent VOH from falling below VOHmin (D) prevent VOL from rising above VOLmax (E) none of the above 23. When a gate’s rated IOL specification is exceeded, the following is likely to happen: (A) the VOH of the gate will increase and the tTLH of the gate will decrease (B) the VOL of the gate will decrease and the tTHL of the gate will increase (C) the VOH of the gate will decrease and the tTLH of the gate will increase (D) the VOL of the gate will increase and the tTHL of the gate will increase (E) none of the above 24. If a CMOS inverter drives a capacitive load of 100 pF and the “on” resistance of its P-channel MOSFET is 20 Ω, then the gate’s output rise time (tTLH) is approximately: (A) 0.2 ns (B) 2 ns (C) 20 ns (D) 2000 ns (E) none of the above