Routers-Computer Networks-Lecture 03 Slides-Computer Science, Slides for Computer Networks. Rutgers University (NJ)
steven005
steven00511 March 2012

Routers-Computer Networks-Lecture 03 Slides-Computer Science, Slides for Computer Networks. Rutgers University (NJ)

PDF (1 MB)
64 pages
13Number of download
1000+Number of visits
Description
Routers, Basic Components, Forwarding Engine, Hardware, First-generation IP Routers, Second-generation IP Routers, Third-generation IP Routers, MGR, Forwarding Speeds, Multihomed Networks, Badri Nath, Lecture Slides, Com...
20 points
Download points needed to download
this document
Download the document
Preview3 pages / 64

This is only a preview

3 shown on 64 pages

Download the document

This is only a preview

3 shown on 64 pages

Download the document

This is only a preview

3 shown on 64 pages

Download the document

This is only a preview

3 shown on 64 pages

Download the document
Microsoft PowerPoint - Week4 [Compatibility Mode]

Computer Networks CS 552

Badri Nath

1

Rutgers University

[email protected]

1. High Speed Routers

2. Route lookups

Routers

2

Cisco 12016: 80 Gbps

Cisco 12416: 320 Gbps

Cisco 12816: 1280 Gbps

Power: 4.2 KW

Juniper M 320

320 Gbps

Power 3.2 KW

What do routers do?

 Routing  Decide the next hop based on Destination

address

 Cost varies as Table size

3

 Header modification  Decrement TTL, compute checksum, Link layer

address for next hop, etc

 Forwarding  Byte movement

 Move bytes from input to output

 Need to keep up with technology

Basic Components

Control Plane Routing Table

Routing Protocols

4

Datapath” per-packet processing

Switching Forwarding

Table

Forwarding Engine

headerpayload

Packet

Router

Routing Lookup

5

Destination Address

Outgoing Port

Dest-network Port

Forwarding Table

Data Structure

65.0.0.0/8

128.9.0.0/16

149.12.0.0/19

3

1

7

Need for high speed routers

 B/W is increasing

 Need to keep line cards fully utilized

Line Linerate 40B Lookup- speed

84B 354B

6

(Gbps) (Mpps) (nano sec) (Mpps) (Mpps)

OC3 0.155 0.48 2083 0.23 0.054

OC12 0.622 1.94 515 0.92 0.22

OC48 2.5 7.81 128 3.72 0.88

OC192 10.0 31.25 32 14.88 3.53

OC768 40.0 125 8 59.52 14.12

Hardware

 DRAM access times 50 nsec

 Pricing: DRAM Yr 2010 :50$ to 100 $ /GB

 In [Gupta 98] 16 MB for 50 $ was the price in 1998

7

 SRAM access times 10 nsec

 Pricing: SRAM 256 to 512 KB is 50$

First-Generation IP routers

CPU Buffer

Memory

8

Line

Card

DMA

MAC

Line

Card

DMA

MAC

Line

Card

DMA

MAC

First-generation IP routers

 Shared memory

 Bus is the bottleneck

 Memory r/w speeds

9

 Every packet needs two transfers between line cards and memory

 Does not scale to too many line cards

 Suffices for Low speed routers

Second-Generation IP routers

CPU Buffer

Memory

10

DMA

MAC

Route

Cache

DMA

MAC

Route

Cache

DMA

MAC

Route

Cache

Fast Path

Slow Path

Cache update

Second-generation IP routers

 Each line card has a route cache

 On a hit, forward directly

 Fast path

On a miss, via CPU bus, memory

11



 Slow path

 Copy only header, then reconstruct packet on outbound link

 Buffer packets on cards

Third -Generation IP routers

TSU FSU FSU

TSU

12

MAC

buffer

Forwarding

Engine

MAC

buffer

Mckeown 97, Partridge 98

Forwarding

Engine

13

Juniper Networks M-Series Routers

Third-generation IP routers

 Switching fabric  Distributed architecture  Multiple forwarding engines  Forwarding engines determine output line based on

header

14

 Can cache route entries  Routing and forwarding separation

 FE determines which outbound line to send the packet  Only header moves between line card and FE  Packet construction and deconstruction done by line cards  Line card uses the switching fabric to forward the packet

MGR

15

 Network Processor, FE processor, Packet Processor  Only header moves around  Two memory banks to handle route updates  Routing table handled by NP (maintains several routes to D)

 Routing Information for various destinations  Determine active routes based on policy

 Forwarding table handled by FEP (maintains only active route to D)  Install active routes for each destination

Router Specification

 Architecture

 15 (input/output) line cards: C = 2.5 Gbps (3.3 Gbps including packet headers)

16

 Each input card can handle up to 16 (input/output) interfaces

 Separate forward engines (FEs) to perform routing

 Backplane: Point-to-point (switched) bus, capacity B = 50 Gbps (32 MPPS)

Router Architecture: Data Plane

 Line cards

 Input processing: can handle input links up to 2.5 Gbps

 Output processing: use a 52 MHz FPGA; implements flow control, scheduling etc

 Forward engine:

17

 415-MHz DEC Alpha 21164 processor, three level cache to store recent routes

 Up to 12,000 routes in second level cache (96 kB); ~ 95% hit rate

 Entire routing table in tertiary cache (16 MB divided in two banks)

Router Architecture: Control Plane

 Network processor: 233-MHz 21064 Alpha running NetBSD 1.1  Update routing

 Manage link status

18

 Implement reservation

 Backplane Allocator: implemented by an FPGA  Schedule transfers between input/output

interfaces

Data Plane Details: Slow Path Processing

1. Headers whose destination misses in the cache

2. Headers with errors

3. Headers with IP options

4. Datagrams that require fragmentation

19

5. Multicast datagrams

 Requires multicast routing which is based on source address and inbound link as well

 Requires multiple copies of header to be sent to different line cards

MGR router: [Partridge 1998] Some observations H/W units

1998 2010

FE Processor

Network Processor

415 Mhz

233 Mhz

? GHZ

Level II cache 1 MB or 2MB

20

Level 1 cache (on-chip) 96KB 256 KB or 512 KB

I-Cache

D-Cache

8KB 8KB 64KB

64 KB

Registers

Switch

32 Registers

15 Port

16 or 32 registers

?

Three types of switching fabrics

21

Forwarding speeds

 Lots of H/W

 Specialized H/W

 Network Processor

Switching fabric

22



 Smart Forwarding (copy only header)

 3rd generation can match line card speeds

Portland

Providence

Cedar

Knolls

Syracuse

Buffalo

White

Plains

Rochester

Las

Salt Lake

City

Milwaukee

Detroit

Seattle Spokane

Portland

Denver

Pittsburgh Plymouth

Minneapolis

Rochelle Pk Hamilton

SquareSilver

Wayn

e

Chicago

Rolling

Meadows

Omaha

Anchorage,

AK

Cambridge

Framingham

Stamford Bridgepo

rt

Grand

Rapids Providence

Glenvie

w

Albany

Sacramento

San

Chicag

oSan

Francisco

Davenport

Worcester

Madison

New

Brunswick Oak

Brook

South Bend

Dayto

Hartford

Harrisbu

rg Des

Moines

R

AkronRR Wash

.DC

St. Paul

Manchester

R R

R

Phil

NY

C

Cleveland

RBirmingham

Year end 2001

AT&T IP Backbone, USA

23

Charlotte

Newark

Columbia

New Orleans

Nashville

Austin

Houston

Tulsa Oklaho

ma

City

Albuquerque

Phoenix

Anaheim

Vegas

Colorado

Springs

Columbus

Cincinnati

Louisville

Little Rock

Jacksonville

Ft.

Lauderdale

Miami

Raleigh

Richmond

Indianapolis Baltimore

Atlanta

Garden

a

Tampa

San

Bernardino

Arlington

Ft. Worth

Honolulu

Orlando

Sherman Oaks

Ojus

Springs

St Louis

San Diego

N X OC48

Backbone Node

Gateway Node

N X DS3 N X OC3

Remote Access Router

R Remote GSR Access Router

N X OC12

NX OC192

Oakland

Redwood

City

San Jose

Francisco

Florissant Camden,

NJ

Norcross Birmingham

San Antonio

n Bohemia

San Juan PR

W. Palm Beach

Memphis

Greensboro

Norfolk

Kansas

City

R

Los Angeles

Dallas

Freehold

R

R R

Ft.

Lauderdale

Dunwoody

Note: Connectivity and nodes shown are targeted for deployment; actual deployment

may vary. Maps should not be used to predict service availability.

R

R NYC-

Bdwy

LA-

Airport

Blvd

Rev. 6-4-01

NTT global IP backbone map

24http://navigators.com/isp.html

Sprint

25

comments (0)

no comments were posted

be the one to write the first!

This is only a preview

3 shown on 64 pages

Download the document