Svpwm for multilevel inverters, Thesis for Power Electronics
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kalyan-kumar

Svpwm for multilevel inverters, Thesis for Power Electronics

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Algorithm based svpwm technique for multilevel inverters
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Chapter - 1

Chapter - 4

AN IMPROVED SPACE VECTOR PULSE WIDTH MODULATION

BASED ALGORITHMS FOR MULTILEVEL INVERTERS

4.1 INTRODUCTION

In the previous chapter, the conventional space vector pulse

width modulation algorithm and a novel approach for the generation

of space vector pulse width modulation for multilevel inverters based

on fractals are presented. But, the number of level increases, the

location of reference voltage vector, optimum switching sequence and

dwelling time calculations and the control algorithm becomes more

and more complex. To improve the performance of the multilevel

inverters, in this chapter an improved space vector pulse width

modulation algorithms are proposed and analyzed.

At first, a qualitative space vector pulse width modulation

algorithm for neutral point clamped multilevel inverter is presented. In

this method the duty cycles of reference voltage vectors are corrected

accordingly for identifying the location of the reference voltage vector

in each region. The appropriate switching sequence of the region and

calculation of the switching ON times for each state is estimated. This

scheme can be extended to high-level inverters. The results have been

presented and analyzed for inverters from two-level to seven-level

inverters. The total harmonic distortion have been calculated and

compared with lower levels also.

Then, an analytical space vector pulse width modulation

method for multi-level VSI is proposed based on the intrinsic relation

118

between multi-level and two-level space vector pulse width

modulation. In this method, the dwelling time of vector calculation is

derived from two-level inverter. By using a linear transformation, the

dwelling time of vectors for two-level VSI can be transformed into

multilevel VSI. A novel classification of voltage vectors is proposed to

determine switching pattern of PWM sequence and used upto the

eleven-level inverter, which can be extended to n-level inverter as well.

Finally, a space vector pulse width modulation algorithm using

decomposition method is presented for seven-level inverter. In this

method, the space vector diagram of the seven-level inverter is

decomposed into six space vector diagrams of four-level inverters. In

turn, each of these six space vector diagrams of four-level inverter is

decomposed into six space vector diagrams of three-level inverters and

each of these six space vector diagrams of three-level inverter are

decomposed into six space vector diagrams of two-level inverters. To

proceed with the switching state determination, the first one of these

hexagons is selected, based on the location of the target voltage

vector. Secondly, the original voltage reference vector is decremented

by the voltage vector that locates the origin of the selected two-level

hexagon. This, then, allows the determination of switching sequence

and calculation of the voltage vector duration to be done in the same

manner as for a conventional two-level inverter. The proposed method

reduces the algorithm complexity and the execution time. It can be

applied to the multi-level inverters above the seven-level also.

119

4.2 A QUALITATIVE SPACE VECTOR PULSE WIDTH MODULATION

ALGORITHM FOR MULTILEVEL INVERTERS

The sector identification can be done by using co-ordinate

transformation of the reference vector into a two dimensional co-

ordinate system. The sector can also be determined by resolving the

reference phase vector along a, b and c axis and by repeated

comparison with discrete phase voltages. After identifying the sector,

the voltage vectors at the vertices of the sector are to be determined.

Once the switching voltage space vectors are determined the switching

sequences can be identified using lookup tables. The calculations of

the duration of the voltage vectors can be simplified by mapping the

identified sector correspond to a sector of two-level inverter. To obtain

optimum switching, the voltage vectors are to be switched for their

respective durations, in a sequence such that only one switching

occurs as the inverter moves from one switching state to another.

The duty cycles of reference voltage vector will be m1, m2 and 1-

(m1+m2). The values of m1 and m2 are useful in identifying the region

where reference vector is located, which is the major problem in case

of multi-level inverters.

In this method, a correction to the duty cycles of reference

vector is applied to easily identify the location of reference vector in

each region of a multilevel inverter. Once the region is identified, the

appropriate switching sequence of the region can be identified. The

ON time period for each state can be calculated with the obtained

duty cycles.

120

4.2.1 Seven-level Neutral Point Clamped Inverter

The circuit diagram and space vector diagram of seven-level

neutral point clamped inverter are as shown in Fig. 4.1 and Fig. 4.2.

In case of seven-level inverter six switches from each phase-leg will be

ON at any point time to produce predetermined output at phases. The

possible switching combinations will be 343 with 216 redundant

states.

Fig. 4.1 Seven-level NPC inverter topology.

The space vector (Vref) constituted by the pole voltages of inverter

Vao, Vbo and Vco with 1200 phase displacement is defined;

3 4πj

co 3

2πj

boaoref .eV.eVVV ++= (4.1)

P

n

V dc2

V dc1

V dc1

V dc3

V dc2

V dc3

b c

a

T a1

T a10

T a9

T a11

T a12

T a4

T a5

T a6

T a7

T a8

T a2

T a3

T b1

T b10

T b9

T b11

T b12

T b4

T b5

T b6

T b7

T b8

T b2

T b3

T c1

T c10

T c9

T c11

T c12

T c4

T c5

T c6

T c7

T c8

T c2

T c3

z

121

The dwelling time periods T1, T2 and T0 are

)3/sin( )3/sin(

1 π× α−π××

= dc

sref

V TV

T (4.2)

)3/sin( sin

2 π× α××

= dc

sref

V TV

T (4.3)

)( 210 TTTT s +−= (4.4)

Fig. 4.2 Space vector diagram of seven-level inverter.

In Multilevel inverters the reference voltage vector can be

reproduced in the average sense by switching amongst the inverter

states situated at the vertices, which are in the closest proximity to it.

In case of two-level inverter, the identification of reference vector

666 555 444 333 222 111 000

655 544 433 322 211 100

644 533 422 311 200

633 522 411 300

622 511 400

611 500

600066

566 455 344 233 122 011

466 355 244 133 022

366 255 144 033

266 155 044

166 055

665 554 443 332 221 110

654 543 432 321 210

643 532 421 310

632 521 410

621 510

610

565 454 343 232 121 010

465 354 243 132 021

365 254 143 032

265 154 043

165 054

065

564 453 342 231 120

664 553 442 331 220

653 542 431 320

642 531 420

631 520

620

464 353 242 131 020

364 253 142 031

264 153 042

164 053

064

563 452 341 230

663 552 441 330

652 541 430

641 530

630 463 352 241 130

363 252 141 030

263 152 041

163 052

063

462 351 240

562 451 340

662 551 440

651 540

640362251 140

262 151 040

162 051

062

461 350

561 450

661 550

650361 250

261 150

161 050

061

060 160 260 360 460 560 660

656 545 434 323 212 101

645 534 423 312 201

634 523 412 301

623 512 401

612 501

601

556 445 334 223 112 001

456 345 234 123 012

356 245 134 023

256 145 034

156 045

056

122

location in a sector is straight forward. However, in higher level

inverter, the existence of more than one number of regions in sector

will require additional mathematical computation to identify the

region where the reference vector is located. The duty cycles (ON time

for each state) will be found by equating volt-seconds of reference

voltage with the nearest three states.

332211 VdVdVdm ++= (4.5)

where d1, d2 and d3 are duty cycles of the nearest voltage vectors

V1, V2 and V3 and ‘m’ is the voltage reference vector.

4.2.1.1 Calculation of duty cycles

The vector states at vertices of each region can be identified

from space vector diagrams. Consider the space vector diagram of

sector-I of Seven-level inverter, shown in Fig. 4.3.

Fig. 4.3 Sector-I of seven-level inverter.

006 106 206 306 406 506 606

416 305

516 405

616 504

605316 205

216 105

116 005

016

426 315 204

526 415 304

626 515 404

625 504

604326215 104

226 115 004

126 015

026

536 425 314 203

636 525 414 303

625 514 403

614 503

603 436 325 214 103

336 225 114 003

236 125 014

136 025

063

546 435 323 213 102

646 535 424 313 202

635 524 413 302

624 513 402

613 502

602

446 335 224 113 002

346 235 124 013

246 135 024

146 035

046

656 545 434 323 212 101

645 534 423 312 201

634 523 412 301

556 445 334 223 112 001

456 345 234 123 012

356 245 134 023

26

30

28

27

34

33 32

31

36

35

m 7

m 6

m 31 m61 m71

m 32

m 72

m 62

0 V/2 VV/6

4

21

1 2 m

3

29

3

123

The reference vector m3 is located in region 2 of three-level

inverter. The m6 and m7 are reference vectors located in region 21 of

six-level inverter and region 29 of seven-level inverter respectively. mx1

and mx2 (x=3 or 6 or 7) are projections of reference vectors on to zero

axis and sixty degrees axis (angle ‘θ’ is angle made by reference vector

from zero axis i.e., starting of sector 1; be noted m3, m6 and m7 have

different angle ‘θ’ value).

The reference vector can be synthesized by sequential switching

operation of nearest three switching states (vertices of the region in

which reference vector is located).

The lengths of new vectors can be found using the equations as

( ) ( )3/sin2

3/sincos

2

1

θ××=

θ−θ×=

mm

mm (4.6)

The values of m1 and m2 for reference vector in each region can

be calculated with Eq. (4.6). The duty cycles of vertices of reference

voltage will be m1, m2 and [1-(m1+m2)]. For example, with reference to

m3 (reference vector in region 2), the reference vector can be

synthesized by switching vectors V1, V2 and V3. It shall be important to

note that duty cycle for switching state V1 shall be length of the vector

joining V3 and V1, whereas, m1 is the projection of reference vector m3

from the origin. As such, the corrected duty cycle for switching state

V1 in present case would be (m1-0.167). The length of vector joining V3

and V2 is m2. As such, corrected duty cycles for switching states V1, V2

and V3 would be (m1-0.167), m2 and (0.833-m1-m2) respectively.

The values of m1 and m2 are useful in identifying the region

where reference vector is located, which is the major problem in

124

multilevel inverters. The conditions for identifying reference vector

location in each region and the corrected duty cycles for each of the

level of inverter are shown in Table 4.1. Once the region is identified,

the appropriate switching sequence of that region can be identified.

The ON time period for each state can be calculated with duty

cycles obtained:

TON for state1 = Ts x m1

TON for state2 = Ts x m2

TON for state3 = Ts x [1- (m1+m2)] (4.7)

4.2.1.2 A Qualitative SVPWM Algorithm

1. Find the sector in which Vref lies.

2. Calculate m1, m2 from Eq. (4.6) and compute (m1+m2) of reference

voltage.

3. Find the region in which Vref is located.

4. Identify the nearest three vectors (vertices of region) of the Vref.

5. Select appropriate switching sequences.

6. Compute ON time for each switching state.

7. Place the inverter states in the respective states for the calculation

of switching ON times.

4.2.1.3 Flowchart

125

Fig. 4.4 Flowchart of qualitative space vector pulse width modulation for multilevel inverter.

Start

Read the inputs: dc voltage (V dc

), reference voltage (V ref

), sampling time (T

s ) and modulation index (m)

Calculate actual V ref

= V dc

* m

Find the sector in which V ref

is located

Calculate lengths of V ref

on -axis and 600 line

Identify the region of V ref

Calculate corrected duty cycles of three vertices of region

Identify the optimum switching sequence

Calculate T 1 , T

2 and T

0 for each

switching state (T s * duty cycle for vector)

Generate control signals for corresponding ON times and place the switches in ON state

End

Is sector completed?

Is cycle completed?

Yes

Yes

No

No

126

4.2.1.4 Location of Reference Vector and Correction of Duty

cycles

The conditions for identifying reference vector location in seven-

level inverter and the corrections required to duty cycles are indicated

in Table 4.1. The switching ON and OFF sequences are as shown in

Table 4.2.

Table 4.1 Location of reference vector and corrected duty cycles

Region Condition for location

of reference vector

Corrected m1, m2 and m3

for switching states

26

0.834<m1<1 ;

m2<0.167;

(m1+ m2)<1

m1= m1-0.833;

m2= m2;

m3=1- m1- m2

27

0.667 < m1<0.834;

m2<0.167 ;

(m1+ m2)>0.834

m1=0.833-m1;

m2=0.167- m2;

m3= m1+ m2-0.834

28

0.667 <m1<0.834;

0.167 < m2<0.333;

(m1+ m2)<1

m1=m1-0.667;

m2=m2-0.167;

m3=1- m1- m2

29

0.5< m1<0.667;

0.167< m2<0.333;

(m1+ m2)>0.834

m1=0.667-m1;

m2=0.333- m2;

m3= m1+ m2-0.834

30

0.5< m1<0.667 ;

0.333< m2<0.5;

(m1+ m2)<1

m1= m1-0.5;

m2= m2-0.333;

m3=1- m1- m2

31

0.333<m1<0.5;

0.333< m2<0.5;

(m1+ m2)>0.834

m1=0.5 -m1;

m2=0.5- m2;

m3= m1+ m2-0.834

32

0.333<m1<0.5;

0.5< m2<0.667;

(m1+ m2)<1

m1= m1-0.333;

m2= m2-0.5;

m3=1- m1- m2

127

33

0.167<m1<0.333;

0.5<m2<0.667;

(m1+m2)>0.834

m1= 0.5-m1;

m2= 0.667-m2;

m3=m1+ m2-0.834

34

0.167<m1<0.333;

0.667<m2<0.834;

(m1+m2)<1

m1= m1-0.167;

m2= m2-0.667;

m3=1- m1- m2

35

m1<0.167;

0.667<m2<0.834;

(m1+m2)>0.834

m1= 0.167-m1.;

m2= 0.834-m2;

m3=m1+ m2-0.834

36

m1<0.167;

0.834<m2<1;

(m1+m2)<1

m1= m1;

m2= m2-0.834;

m3=1- m1- m2

Table 4.2 Switching sequence of seven-level inverter

Sector Region ON Sequence OFF Sequence

1 26 500 600 610 611 611 610 600 500

27 500 510 610 611 611 610 510 500

28 510 610 620 621 621 620 610 510

29 510 520 620 621 621 620 520 510

30 520 620 630 631 631 630 620 520

31 520 530 630 631 631 630 530 520

32 530 630 640 641 641 640 630 530

33 530 540 640 641 641 640 540 530

34 540 640 650 651 651 650 640 540

35 540 550 650 651 651 650 550 540

36 550 650 660 661 661 660 650 550

2 47 050 060 160 161 161 160 060 050

46 050 150 160 161 161 160 150 050

45 150 160 260 261 261 260 160 150

44 150 250 260 261 261 260 250 150

43 250 260 360 361 361 360 260 250

128

42 250 350 360 361 361 360 350 250

41 350 360 460 461 461 460 360 350

40 350 450 460 461 461 460 450 350

39 450 460 560 561 561 560 460 450

38 450 550 560 561 561 560 550 450

37 550 560 660 661 661 660 560 550

3 48 050 060 061 161 161 061 060 050

49 050 051 061 161 161 061 051 050

50 051 061 062 162 162 062 061 051

51 051 052 062 162 162 062 052 051

52 052 062 063 163 163 063 062 052

53 052 053 063 163 163 063 053 052

54 053 063 064 164 164 064 063 053

55 053 054 064 164 164 064 054 053

56 054 064 065 165 165 065 064 054

57 054 055 065 165 165 065 055 054

58 055 065 066 166 166 066 065 055

4 69 005 006 016 116 116 016 006 005

68 005 015 016 116 116 016 015 005

67 015 016 026 126 126 026 016 015

66 015 025 026 126 126 026 025 015

65 025 026 036 136 136 036 026 025

64 025 035 036 136 136 036 035 025

63 035 036 043 146 146 043 036 035

62 035 045 043 146 146 043 045 035

61 045 046 056 156 156 056 046 045

60 045 055 056 156 156 056 055 045

59 055 056 066 166 166 066 056 055

5 70 005 006 106 116 116 106 006 005

71 005 105 106 116 116 106 105 005

129

72 105 106 206 216 216 206 106 105

73 105 205 206 216 216 206 205 105

74 205 206 306 316 316 306 206 205

75 205 305 306 316 316 306 305 205

76 305 306 406 416 416 406 306 305

77 305 405 406 416 416 406 405 305

78 405 406 506 516 516 506 406 405

79 405 505 506 516 516 506 505 405

80 505 506 606 616 616 606 506 505

6 91 500 600 601 611 611 601 600 500

90 500 501 601 611 611 601 501 500

89 501 601 602 612 612 602 601 501

88 501 502 602 612 612 602 502 501

87 502 602 603 613 613 603 602 502

86 502 503 603 613 613 603 503 502

85 503 603 604 614 614 604 603 503

84 503 504 604 614 614 604 504 503

83 504 604 605 615 615 605 604 504

82 504 505 605 615 615 605 505 504

81 505 605 606 616 616 606 605 505

4.2.2 Results and Discussions

To validate the proposed qualitative space vector pulse width

modulation algorithm for multilevel inverters, the simulation studies

have been carried out for two-level, three-level, four-level, five-level,

six-level and seven-level inverters. The simulation parameters and

specifications of induction motor used in this method are given in

Appendix-III. The results for two-level inverter are shown in Fig. 4.5 to

Fig. 4.10. The phase voltages and line voltages of two-level inverter are

130

shown in Fig. 4.5 and Fig. 4.6. The output line voltage and its

harmonic spectrum are shown in Fig. 4.7. The stator currents, rotor

speed and torque responses of two-level inverter fed induction motor

are shown in Fig. 4.8 to Fig. 4.10. The results for three-level inverter

are shown in Fig. 4.11 to Fig. 4.16. The phase and line voltages are

shown in fig. 4.11 and Fig. 4.12. The output line voltage and its

harmonic spectrum are shown in Fig. 4.13. The stator currents, rotor

speed and torque responses of three-level inverter fed induction motor

are shown in Fig. 4.14 to Fig. 4.16. The results of four-level inverter

are shown in Fig. 4.17 to Fig. 4.22. The phase voltages, line voltages,

output line voltage and its harmonic spectrum are shown in Fig. 4.17

to Fig.4.19. The stator currents, rotor speed and torque responses of

four-level inverter fed induction motor are shown in Fig. 4.20 to Fig.

4.22. The results of five-level inverter are shown in Fig. 4.23 to Fig.

4.28. The phase voltages, line voltages, output voltage harmonic

spectrum and THD are shown in Fig. 4.23 to Fig.4.25. The stator

currents, rotor speed and torque of five-level inverter fed induction

motor are shown in Fig. 4.26 to Fig. 4.28. The results of six-level

inverter are shown in Fig. 4.29 to Fig. 4.34. The phase voltages, line

voltages, output line voltage and its harmonic spectrum are shown in

Fig. 4.29 to Fig.4.31. The stator currents, rotor speed and torque

responses of six-level inverter fed induction motor are shown in Fig.

4.32 to Fig. 4.34. The results of seven-level inverter are shown in Fig.

4.35 to Fig. 4.40. The phase voltages, line voltages and its harmonic

spectrum are shown in Fig. 4.35 to Fig.4.37. The stator currents, rotor

131

speed and torque responses of seven-level inverter fed induction motor

are shown in Fig. 4.38 to Fig. 4.40 The output line voltage harmonic

spectrum of two-level, three-level, four-level, five-level, six-level and

seven-level inverters are shown in Fig. 4.7, Fig. 4.13, Fig. 4.19, Fig.

4.25, Fig. 4.31 and Fig. 4.37 respectively which show the reduction of

THD with increase level of inverter. The improvement in the stator

currents of two-level, three-level, four-level, five-level, six-level and

seven-level inverter fed induction motor is shown in Fig. 4.8, Fig. 4.14,

Fig. 4.20, Fig. 4.26, Fig. 4.32 and Fig. 4.38 respectively. The torque

response of two-level, three-level, four-level, five-level, six-level and

seven-level inverter fed induction motor can be observed in Fig. 4.10,

Fig. 4.16, Fig. 4.22, Fig. 4.28, Fig. 4.34 and Fig. 4.40. From these

results, it is observed that as the level of the inverter is increased, the

THD is decreased and torque ripples also greatly reduced.

4.2.2.1 Two-level Inverter

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -300

-150

0

150

300

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -300

-150

0

150

300

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -300

-150 0

150 300

Time (s)

P ha

se v

ol ta

ge s

V an

, V bn

, V cn

( V

)

Fig. 4.5 Phase voltages of two-level inverter.

132

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -400

-200

0

200

400

Li ne

v ol

ta ge

s V

ab , V

bc , V

ca (

V )

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -400

-200

0

200

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -400

-200

0

200

400

Time (s)

Fig. 4.6 Line-to-line voltages of two-level inverter.

0 0.02 0.04 0.06 0.08 -400

-200

0

200

400

Time (s)

FFT window: 5 of 50 cycles of selected signal

0 200 400 600 800 1000 0

5

10

15

20

25

Frequency (Hz)

Fundamental (50Hz) = 341.6 , THD= 42.48%

M ag

( %

o f F

un da

m en

ta l)

Fig. 4.7 Output line voltage and its harmonic spectrum of two-level inverter.

133

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -60

-40

-20

0

20

40

60

Time (S)

S ta

to r

cu rr

en ts

Ia s,

Ib s,

Ic s

(A )

Fig. 4.8 Stator currents of two-level inverter fed induction motor.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

20

40

60

80

100

120

140

160

Time (s)

R ot

or s

pe ed

W m

( ra

d/ s)

Fig. 4.9 Speed response of two-level inverter fed induction motor.

134

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -10

0

10

20

30

40

50

60

70

Time (s)

T or

qu e

T e

(N -m

)

Fig. 4.10 Torque response of two-level inverter fed induction motor.

4.2.2.2 Three-level Inverter

Fig. 4.11 Phase voltages of three-level inverter.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -300

-150

0

150

300

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -300

-150

0

150

300

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -300

-150

0

150

300

Time (s)

Phase voltages Van, Vbn, Vcn (V)

135

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -400

-200

0

200

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -400

-200

0

200

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -400

-200

0

200

400

Time (s)

Li ne

v ol

ta ge

s V

ab , V

bc , V

ca (

V )

Fig. 4.12 Line-to-voltages of three-level inverter.

0 0.02 0.04 0.06 0.08 -400

-200

0

200

400

Time (s)

FFT window: 5 of 50 cycles of selected signal

0 200 400 600 800 1000 0

2

4

6

8

10

12

Frequency (Hz)

Fundamental (50Hz) = 306.4 , THD= 24.99%

M ag

( %

o f F

un da

m en

ta l)

Fig. 4.13 Output line voltage and its harmonic spectrum of three-level inverter.

136

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -60

-40

-20

0

20

40

60

Time (S)

S ta

to r

cu rr

en ts

Ia s,

Ib s,

Ic s

(A )

Fig. 4.14 Stator currents of three-level inverter fed induction motor.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

20

40

60

80

100

120

140

160

Time (s)

R ot

or s

pe ed

W m

( ra

d/ s)

Fig. 4.15 Speed response of three-level inverter fed induction motor.

137

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -10

0

10

20

30

40

50

Time (s)

<Electromagnetic torque Te (N*m)>

T or

qu e

T e

(N -m

)

Fig. 4.16 Torque response of three-level inverter fed induction motor.

4.2.2.3 Four-level Inverter

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -300

-150

0

150

300

P ha

se v

ol ta

ge s

V an

, V bn

, V cn

( V

)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -300

-150

0

150

300

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -300

-150

0

150

300

Time (s)

Fig. 4.17 Phase voltages of four-level inverter.

138

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -400

-200

0

200

400

Li ne

v ol

ta ge

s V

ab , V

bc , V

ca (

V )

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -400

-200

0

200

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -400

-200

0

200

400

Time (s)

Fig. 4.18 Line-to line voltages of four-level inverter.

0 0.02 0.04 0.06 0.08 -400

-200

0

200

400

Time (s)

FFT window: 5 of 50 cycles of selected signal

0 200 400 600 800 1000 0

2

4

6

8

Frequency (Hz)

Fundamental (50Hz) = 332.1 , THD= 17.05%

M ag

( %

o f F

un da

m en

ta l)

Fig. 4.19 Output line voltage and its harmonic spectrum of four-level inverter.

139

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -60

-40

-20

0

20

40

60

Time (S)

S ta

to r

cu rr

en ts

Ia s,

Ib s,

Ic s

(A )

Fig. 4.20 Stator currents of four-level inverter fed induction motor.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0

20

40

60

80

100

120

140

160

Time (s)

R ot

or s

pe ed

W m

( ra

d/ s)

Fig. 4.21 Speed response of four-level inverter fed induction motor.

140

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -10

0

10

20

30

40

50

60

Time (s)

T or

qu e

T e

(N -m

)

Fig. 4.22 Torque response of four-level inverter fed induction motor.

4.2.2.4 Five-level Inverter:

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -300

-150

0

150

300

P ha

se v

ol ta

ge s

V an

, V bn

, V cn

( V

)

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -300

-150

0

150

300

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -300

-150

0

150

300

Time (s)

Fig. 4.23 Phase voltages of five-level inverter.

141

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -400

-200

0

200

400

Li ne

v ol

ta ge

s V

ab , V

bc , V

ca (

V )

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -400

-200

0

200

400

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 -400

-200

0

200

400

Time (s)

Fig. 4.24 Line-to-line voltages of five-level inverter.

0 0.02 0.04 0.06 0.08 -400

-200

0

200

400

Time (s)

FFT window: 5 of 50 cycles of selected signal

0 200 400 600 800 1000 0

1

2

3

4

5

6

Frequency (Hz)

Fundamental (50Hz) = 198.3 , THD= 11.57%

M ag

( %

o f F

un da

m en

ta l)

Fig. 4.25 Output line voltage and its harmonic spectrum of five-level inverter.

142

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