Switching techlonogies, Thesis for Telecommunication electronics
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bhaskar9490188696

Switching techlonogies, Thesis for Telecommunication electronics

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Switching technologies introduction
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Part I: Introduction

#1

Switching Units

#2

Types of switching elements  Telephone switches

 switch samples Datagram routers

 switch datagrams ATM switches

 switch ATM cells

INPUTS

OUTPUTS

#33

Look Inside a Router Two key router functions:  run routing algorithms/protocol (RIP, OSPF, BGP)  switching datagrams from incoming to outgoing ports

#4

Repeaters, bridges, routers, and gateways  Repeaters/Hubs: at physical level (L1)  Bridges: at datalink level (L2)

 based on MAC addresses  discover attached stations by listening

 Routers: at network level (L3)  participate in routing protocols

 Application level gateways: at application level (L7)  treat entire network as a single hop

 Gain functionality at the expense of forwarding speed  for best performance, push functionality as low as

possible

#5

Types of services  Packet vs. circuit switches

 packets have headers and samples don’t Connectionless vs. connection oriented

 connection oriented switches need a call setup

 setup is handled in control plane by switch controller

 connectionless switches deal with self- contained datagrams

#6

Other switching unit functions  Participate in routing algorithms

 to build routing tables  Next Lecture!

Resolve contention for output trunks  buffer scheduling  Previous Lecture!

Admission control  to guarantee resources to certain streams

#7

Requirements  Capacity of switch is the maximum rate at

which it can move information, assuming all data paths are simultaneously active

 Primary goal: maximize capacity  subject to cost and reliability constraints

 Circuit switch must reject call if can’t find a path for samples from input to output  goal: minimize call blocking

 Packet switch must reject a packet if it can’t find a buffer to store it awaiting access to output trunk  goal: minimize packet loss

 Subgoal: Don’t reorder packets

#8

Internal switching  In a circuit switch, path of a sample is determined

at time of connection establishment  No need for a sample header--position in frame is enough

 In a packet switch, packets carry a destination field  Need to look up destination port on-the-fly

 Datagram  lookup based on entire destination address

 Cell  lookup based on VCI – used as an index to a table

 Other than that, switching units are very similar

#9

Blocking in packet switches Can have both internal and output

blocking  Internal

 no path to output  Example: head of line blocking.

Output  output link busy

 If packet is blocked, must either buffer or drop it

#10

Dealing with blocking Overprovisioning

 internal links much faster than inputs Buffers

 at input or output Backpressure

 if switch fabric doesn’t have buffers, prevent packet from entering until path is available

 Parallel switch fabrics  increases effective switching capacity

#11

Three generations of packet switches Different trade-offs between cost and

performance Represent evolution in switching

capacity, rather than in technology  With same technology, a later generation

switch achieves greater capacity, but at greater cost

All three generations are represented in current products

#12

First generation switch

Most Ethernet switches and cheap packet routers

Bottleneck can be CPU, host-adaptor or I/O bus, depending

computer

queues in memory

CPU

linecard linecard linecard

#13

Second generation switch

 Port mapping intelligence in line cards Bottleneck is the bus (or ring)

bus

computer

front end processors or line cards

#14

Third generation switches  Third generation switch provides

parallel paths (fabric)

NxN packet switch fabric

OLC

OLC

OLC

IN

ILC

ILC

ILC

OUT

control

#15

Third generation (contd.)  Features

 self-routing fabric  output buffer is a point of contention

• unless we arbitrate access to fabric  potential for unlimited scaling,

• as long as we can resolve contention for output buffer

#16

Switching - Fabric

#17

Switching: abstract model

Number of connections: from few (4 or 8) to huge (100K)

#18

Multiplexors and demultiplexors Multiplexor: aggregates sessions

 N input lines  Output runs N times as fast as input

Demultiplexor: distributes sessions  one input line and N outputs that run N

times slower Can cascade multiplexors

De-Mux

1 2

N

1 2

N

1 2 NMUX

#19

Time division switching Key idea: when demultiplexing, position

in frame determines output link  Time division switching interchanges

sample position within a frame:  Time slot interchange (TSI)

M U X

D E M U X

TSI

#20

Time Slot Interchange (TSI) : example

sessions: (1,3) (2,1) (3,4) (4,2)

4 3 2 1 3 1 4 2

1 2 3 4

Read and write to shared memory in different order

1

2 3

4

2

4 1

3

#21

TSI  Simple to build.  Multicast: easy (why?)  Limit is the time taken to read and write to

memory  For 120,000 telephone circuits

 Each circuit reads and writes memory once every 125 ms.

 Number of operations per second : 120,000 x 8000 x2  each operation takes around 0.5 ns => impossible with

current technology  Need to look to other techniques

#22

Space division switching  Each sample takes a

different path through the switch, depending on its destination

Crossbar: Simplest possible space- division switch

Crosspoints can be turned on or off

i n p u t s

outputs

#23

Crossbar - example

1 2 3

4

1 2 3 4

sessions: (1,2) (2,4) (3,1) (4,3)

in pu

ts

output

#24

Crossbar Advantages:

 simple to implement  simple control  strict sense non-blocking  Multicast

• Single source multiple destination ports Drawbacks

 number of crosspoints, N2  large VLSI space  vulnerable to single faults

#25

Time-space switching  Precede each input trunk in a crossbar

with a TSI Delay samples so that they arrive at the

right time for the space division switch’s schedule Crosspoint: 4 (not 16)

memory speed : x2 (not x4)

2 1

4 3

M U X M U X

1

2 3

4

TSI

TSI

1 2

4 3

DeMux DeMux

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