VTU 4TH SEM CSE MICROPROCESSORS NOTES 10CS45, Study notes for Microprocessors. Visvesvaraya Technological University

VTU 4TH SEM CSE MICROPROCESSORS NOTES 10CS45, Study notes for Microprocessors. Visvesvaraya Technological University

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Subject Code: 10CS45 I.A. Marks : 25

Hours/Week : 04 Exam Hours: 03

Total Hours : 52 Exam Marks: 100


UNIT – 1 7 Hours

Introduction, Microprocessor Architecture – 1: A Historical Background, The Microprocessor-Based Personal

Computer Systems.

The Microprocessor and its Architecture: Internal Microprocessor Architecture, Real Mode Memory Addressing.

UNIT – 2 7 Hours

Microprocessor Architecture – 2, Addressing Modes: Introduction to Protected Mode Memory Addressing,

Memory Paging, Flat Mode Memory

Addressing Modes: Data Addressing Modes, Program Memory Addressing Modes, Stack Memory Addressing


UNIT – 3 6 Hours

Programming – 1: Data Movement Instructions: MOV Revisited, PUSH/POP, Load-Effective Address, String

Data Transfers, Miscellaneous Data Transfer Instructions, Segment Override Prefix, Assembler Details.

Arithmetic and Logic Instructions: Addition, Subtraction and Comparison, Multiplication and Division.

UNIT - 4 6 Hours

Programming – 2: Arithmetic and Logic Instructions (continued): BCD and ASCII Arithmetic, Basic Logic

Instructions, Shift and Rotate, String Comparisons.

Program Control Instructions: The Jump Group, Controlling the Flow of the Program, Procedures, Introduction to

Interrupts, Machine Control and Miscellaneous Instructions.


UNIT - 5 6 Hours

Programming – 3: Combining Assembly Language with C/C++: Using Assembly Language with C/C++ for 16-

Bit DOS Applications and 32-Bit Applications

Modular Programming, Using the Keyboard and Video Display, Data Conversions, Example Programs

UNIT - 6 7 Hours

Hardware Specifications, Memory Interface – 1: Pin-Outs and the Pin Functions, Clock Generator, Bus

Buffering and Latching, Bus Timings, Ready and Wait State, Minimum versus Maximum Mode.

Memory Interfacing: Memory Devices

UNIT – 7 6 Hours

Memory Interface – 2, I/O Interface – 1: Memory Interfacing (continued): Address Decoding, 8088 Memory

Interface, 8086 Memory Interface.

Basic I/O Interface: Introduction to I/O Interface, I/O Port Address Decoding.

UNIT 8 7 Hours

I/O Interface – 2, Interrupts, and DMA: I/O Interface (continued): The Programmable Peripheral Interface

82C55, Programmable Interval Timer 8254.

Interrupts: Basic Interrupt Processing, Hardware Interrupts: INTR and INTA/; Direct Memory Access: Basic DMA

Operation and Definition.

Text Book:

1. Barry B Brey: The Intel Microprocessors, 8th Edition, Pearson Education, 2009. (Listed topics only from the Chapters 1 to 13)







The Microprocessor-Based Personal Computer System

• The block diagram of personal-computer is composed of 3 blocks that are interconnected by buses: 1) Memory system

2) Microprocessor and 3) I/O system (Figure 1-6).

• A bus is the set of common connections that carry the same type of information.

Figure 1-6: The block diagram of a microprocessor-based computer system



The Memory & I/O System

• Normally, the memory contains 3 main parts: 1) TPA(Transient Program Area)

2) System Area & 3) XMS(Extended Memory System)

• If the computer is based upon 8086, the TPA and system-area exist, but there is no extended memory-area(Fig:1-7).

• The PC contains → 640KB of TPA & → 384KB of system memory

• The first 1Mbyte of memory is called real(conventional) memory because each microprocessor is designed to function in this area by using its real-mode of operation.

• If the computer is based upon 80286, then 1)TPA 2)System area 3)Extended memory exist. These machines are called AT class-machines. (Sometimes, these machines are also referred to as ISA machines <Industry Standard Architecture>)

• In the 80286, extended-memory contains up to 15MB (in addition to the first 1Mbyte of real memory).

• The ISA machine contains an 8-bit peripheral-bus. The bus is used to interface 8-bit devices to the 8086-based computer.

• In ATX class-systems, following 3 newer buses exist: 1) USB(Universal Serial Bus) is used to connect peripheral-devices( such as keyboards and mouse) to the microprocessor through a serial data-path and a twisted-pair of wires. (Main idea: To reduce system cost by reducing the number of wires).

2) AGP(Advanced Graphics Port) is used to transfer data between the video-card and the microprocessor at higher speeds(533 MB/s) 3) SATA(Serial ATA) is used to transfer data from the PC to the hard-disk drive at rate of 150MB/s.

Figure 1-7: The memory map of a personal computer



TPA (Transient Program Area)

• This holds i)DOS, ii)Application-programs and iii)Drivers that control the computer.

• Length of TPA = 640KB (Fig: 1-8).

• The memory-map of TPA contain following parts: 1) The Interrupt-vectors access various features of the DOS, BIOS and applications. 2) The system BIOS is a collection of programs stored in either a ROM or flash memory. This operates many of the I/O devices connected to the computer. 3) The DOS communications areas contain transient-data used by programs to access → I/O devices and → internal features of the computer.

4) The IO.SYS contains programs that allow DOS to use the keyboard, video-display, printer and other I/O devices. 5) Device-drivers are programs that control installable I/O devices such as mouse, keyboard, CD-ROM

memory, DVD. 6) The COMMAND.COM program(command processor) controls the operation of the computer from the keyboard when operated in the DOS mode.

The System Area

• This contains memory used for video-cards, disk-drives and the BIOS ROM.

• This contains → programs on either a ROM or flash memory & → areas of RAM for data-storage.

• The area at locations C8000H-DFFFFH is open(or free). This area is used for the expanded memory system(EMS) in the computer.

• The EMS allows a 64Kbyte page-frame of memory to be used by application-programs.

• Finally, the system BIOS ROM controls the operation of the basic I/O devices connected to the computer.

Figure 1-8:The memory map of the TPA in a PC Figure 1-9:The system area of a typical PC



I/O Space

• An I/O port is similar to a memory-address, except that instead of addressing memory, it addresses an I/O device.

• The I/O devices allow the microprocessor to communicate between itself and the outside world.

• The I/O space extends from I/O port 0000H to port FFFFH.

• The I/O space allows the computer to access → up to 64 different 8-bit I/O devices or

→ up to 32K different 16-bit devices.

The Microprocessor

• The microprocessor(or CPU) is the controlling-element in a computer.

• The microprocessor controls memory and I/O through buses.

• Memory and I/O are controlled through instructions that are → stored in the memory and

→ executed by the microprocessor

• The buses → select an I/O or memory-device → transfer data between an I/O(or memory) and the microprocessor &

→ control the I/O and memory.

• The microprocessor performs 3 main tasks for the computer: 1) Data transfer between itself and the memory or I/O 2) Simple arithmetic & logic operations 3) Program flow via simple decisions

• The microprocessor executes programs(stored in the memory) to perform complex operations in short periods of time. (The arithmetic and logic operations are very basic, but through them, very complex problems are solved).

• Data are operated upon from the memory or internal registers. Data widths are variable and include a byte(8 bits) and word(16 bits).

• Microprocessor is powerful because of its ability to make simple decisions based upon numerical facts.

• Simple arithmetic and logic operations includes: Addition, Subtraction, Multiplication, Division, AND, OR, NOT, Shift & Rotate

• Decisions found in the 8086 microprocessor are → Zero: Test a number for zero or not-zero

→ Sign: Test a number for positive or negative → Carry: Test for a carry after addition or a borrow after subtraction → Parity: Test a number for an even or an odd number of 1's




• A bus is a common group of wires that interconnect components in a computer (Fig 1-12)

• The buses transfer address-, data- and control-information between → microprocessor & its memory → microprocessor & I/O

• Three types of buses are used for transfer of information: i)address, ii)data and iii)control. Address Bus

• The address-bus is used to request → a memory-location(from the memory) or → an I/O location(from the I/O devices)

• If I/O is addressed, the address-bus contains a 16-bit I/O address. The 16-bit I/O address (or port number) selects one of 64K different I/O devices.

• If memory is addressed, the address-bus contains a memory-address (which varies in width with the different versions of the microprocessor).

• 8086 address 1M byte of memory using a 20-bit address that selects locations 00000H-FFFFFH. 80286 address 16MB of memory using a 24-bit address that selects locations 000000H-FFFFFFH.

Data Bus

• The data bus is used to transfer information between → microprocessor and memory

→ microprocessor and I/O address-space.

• A 16-bit data bus transfers 16 bits of data at a time.

• The advantage of a wider data bus is speed in applications that use wide data.(For example, if a 32 bit number is stored in memory, it takes the 8086 microprocessor two transfer operations to complete because its data bus is only 16 bits wide). Control Bus

• The control-bus → controls the memory & I/O and

→ requests reading or writing of data

• There are 4 control-bus connections: 1) CDRM (memory read control),

2) CTWM (memory write control),


(I/O read control) and

4) CWOI (I/O write control) {The overbar indicates that the control signal is active-low i.e. it is active

when a logic zero appears on the control line. For example, if CWOI =0, the microprocessor is writing data

from the data bus to an I/O device whose address appears on the address bus}

• Steps to read (or fetch) data from memory: 1) Firstly, microprocessor sends an address (of a memory-location) through the address bus to the memory 2) Next, it sends the MRDC signal to cause the memory read data 3) Finally, the data read from the memory are passed to the microprocessor through the data bus

Figure 1-12: The block diagram of a computer system showing the address, data and control bus structure



The Intel family of microprocessor bus and memory sizes

Microprocessor Data bus width Address bus width Memory size

8088 8 20 1M

8086 16 20 1M

80286 16 24 16M

80386DX 32 24 4G

Pentium 64 32 4G

Pentium Pro Core2

64 40 1T

Itanium 128 40 1T

Figure 1-13: The physical memory systems of the 8086 and 80286

Binary Coded Hexadecimal (BCH)

• This is used to represent hexadecimal data in binary-code.

• A binary-coded hexadecimal number is a hexadecimal number written so that each digit is represented by a 4- bit number.

• The assembler is a program that is used to program a computer in its native binary machine language.

• Hexadecimal memory addresses (memory locations) are used to number each byte of the memory system. A hexadecimal number is a number represented in base 16, with each digit representing a value from 0 to 9 and A to F Hexadecimal digit =>BCH code 0=> 0000 1=> 0001 2=> 0010 3=> 0011 4=> 0100 5=> 0101 6=> 0110 7=> 0111 8=>1000 9=>1001 A=>1010 B=>1011 C =>1100 D=>1101 E=> 1110 F=> 1111 Example 1:

2AC =>0010 1010 1100 1000 0011 1101 . 1110 =>83D.E





Internal Microprocessor Architecture The Programming Model

• The programming model of the 8086 is considered to be program-visible because its registers → are used during application programming and

→ are specified by the instructions.

• Other registers are considered to be program-invisible because they are not addressable directly during applications programming, but may be used indirectly during system programming.

• Only 80286 contain the program-invisible registers used to control and operate the protected memory system and other features of the microprocessor.

• The programming model contains 8-, 16- and 32-bit registers.

• The 8-bit registers are AH, AL, BH, BL, CH, CL, DH and Dl. (For example, an ADD AL,AH instruction adds the 8- bit contents of AH to AL)

• The 16-bit registers are AX, BX, CX, DX, SP, BP, DI and SI (AX contains AH and AL)

• The segment registers are CS, DS, ES and SS.

• The 32-bit extended registers are EAX, EBX, ECX, EDX, ESP, EBP, EDI and ESI.

• The 32-bit registers are called multipurpose registers because they hold various data-sizes (bytes, words) and are used for almost any purpose.

• The 64-bit registers are designated as RAX, RBX and so on.

• There are also additional 64-bit registers that are called R8 through R15.

Figure 2-1: The programming model of 8086 through Core2 microprocessor



Multipurpose Registers RAX(Accumulator)

• AX is used for instructions such as multiplication & division instructions (Figure 2-1).

• In 80386, the EAX may also hold the offset-address of a location in the memory. RBX(Base Index)

• BX holds the offset address of a location in the memory.

• In 80386, EBX also can address memory-data. RCX(Count)

• CX holds the count for various instructions.

• The shift & rotate instructions use CL as the count the repeated string & loop instructions use CX as the count.


• DX holds → a part of the result from a multiplication or → a part of the dividend before a division

RBP(Base Pointer)

• BP points to a memory-location for memory data-transfers. RDI(destination Index)

• DI addresses string destination-data for the string instructions. RSI(Source Index)

• SI addresses source string-data for the string instructions. R8 through R15

• These are only found in the Pentium if 64-bit extensions are enabled.

Special Purpose Registers RIP(Instruction Pointer)

• It is used by the microprocessor to find the next sequential instruction in a program located within the code- segment.

• It can be modified with a jump or a call instruction. RSP(Stack Pointer)

• It addresses an area-of-memory called the stack.

• The stack-memory stores data through this pointer.

Segment Registers

• Segment-registers generate memory-addresses when combined with other registers. CS(Code)

• The code-segment is a section-of-memory that holds the code(programs & procedures) used by the microprocessor.

• CS register contains the starting-address of the code-segment.

• In real-mode operation, it defines the start of a 64Kbyte code-segment. In protected-mode, it selects a descriptor that describes the starting-address and length of a code- segment memory.

• The code-segment is limited to → 64 KB in the 8086 and → 4 GB in the 80386


• The data-segment is a section-of-memory that contains most data used by a program.

• Data are accessed in the data-segment by an offset-address (or the contents of other registers that hold the offset-address). ES(Extra)

• The extra-segment is an additional data-segment that is used by some of the string instructions to hold destination-data. SS(Stack)

• The stack-segment is a section-of-memory used for the stack.

• The stack entry-point is determined by the stack-segment(SS) and stack-pointer(SP) registers. FS and GS

• The FS and GS segments allow 2 additional memory segments for access by programs in 80386 microprocessor.




• This register indicates the condition of the microprocessor and controls its operation (Figure 2-2).

Figure 2-2:The EFLAG register of microprocessor family


• Carry holds the carry after addition or the borrow after subtraction.

• The carry flag also indicates error conditions (as dictated by some programs and procedures). P(Parity)

• Parity is logic 0 for odd-parity and logic 1 for even-parity.

• Parity is the count of 1s in a binary-number expressed as even or odd. For example, if a number contains three binary 1 bits, it has odd-parity. A(Auxiliary Carry)

• The auxiliary-carry holds the carry after addition (or borrow after subtraction) between bit-positions 3 and 4 of the result.

• This flag bit is tested by the DAA or DAS instructions to adjust the value of AL after a BCD addition or subtraction. Z(Zero)

• Zero flag shows that the result of an arithmetic or logic operation is zero. If Z=1, the result is zero; if Z=0, the result is not zero.


• Sign flag holds the sign of the result after an arithmetic or logic instruction executes. If S=1, the sign bit is set(or negative); if S=0,the sign bit is cleared(or positive). T(Trap)

• If T=1, the microprocessor interrupts the flow of the program on conditions as indicated by the debug registers and control registers. If the T=0, the trapping feature is disabled.


• This flag controls the operation of the INTR(interrupt request) input pin. If I=1, the INTR pin is enabled; if I=0, the INTR pin is disabled.

• The I flag is set with STI(set I flag) and cleared with the CLI(clear I flag) instructions. D(Direction)

• The direction flag selects either the increment or decrement mode for the DI or SI registers during string instructions.

• If D=1, registers are automatically decremented; if D=0, registers are automatically incremented.

• The D flag is set with STD(set direction) and cleared with the CLI(clear direction) instructions. O(Overflow)

• Overflows occur when signed-numbers are added or subtracted.

• An overflow indicates that the result has exceeded the capacity of the machine. IOPL(I/O Privileged Level)

• IOPL is used to select the privilege-level for I/O devices.

• If current privilege-level is higher or more trusted than the IOPL, I/O executes without difficulty. If current privilege-level is lower than the IOPL, an interrupt occurs, causing execution to suspend. NT(Nested Task)

• This flag indicates that the current task is nested within another task. RF(Resume)

• This flag is used with debugging to control the resumption of execution after the next instruction. VM(Virtual Mode)

• This flag selects virtual mode operation. AC(Alignment Check)

• This flag activates if a word is addressed on a non-word boundary. VIF(Virtual Interrupt)

• This is a copy of the interrupt flag bit available to the Pentium4 microprocessor. VIP(Virtual Interrupt Pending)

• This is used in multitasking environments to provide the operating-system with virtual interrupt flags and interrupt pending information. ID(Identification)

• This flag indicates that the Pentium4 microprocessor supports the CPUID instruction.



Real Mode Memory Addressing

• Real-mode operation allows the microprocessor to address only first 1Mbyte of memory-space. (The first 1M byte of memory is called the real memory, conventional memory or DOS memory system). Segments & Offsets

• In real mode, a combination of a segment-address and an offset-address accesses a memory-location(Figure 2- 3).

• The segment-address (located within one of the segment registers) defines the starting-address of any 64Kbyte memory-segment.

`The offset-address selects any location within the 64KB memory segment.

• Segments always have a length of 64KB. • Each segment-register is internally appended with a 0H on its rightmost end. This forms a 20-bit memory- address, allowing it to access the start of a segment. (For example, when a segment register contains 1200H, it

addresses a 64Kbyte memory segment beginning at location 12000H).

• Because of the internally appended 0H, real-mode segments can begin only at a 16byte boundary in the memory. This 16-byte boundary is called a paragraph.

• Because a real-mode segment of memory is 64K in length, once the beginning address is known, the ending address is found by adding FFFFH.

• The offset-address is added to the start of the segment to address a memory location within the memory- segment. (For example, if the segment address is 1000H and the offset address is 2000H,the microprocessor addresses memory location 12000H).

• In the 80286, an extra 64K minus 16bytes of memory is addressable when the segment is FFFFH and the HIMEM.SYS driver for DOS is installed in the system. This area of memory is referred to as high memory.

Figure 2-3: The real mode memory-addressing scheme using a segment address plus an offset

Default Segment & Offset Registers

• The microprocessor has a set of rules that apply to segments whenever memory is addressed. These rules define the segment-register and offset-register combination. For example, the CS register is always used with the IP to address the next instruction in a program.

• The CS register defines the start of the code-segment and the IP locates the next instruction within the code- segment. For example, if CS=1400H and IP=1200H, the microprocessor fetches its next instruction from memory location 14000H+1200H=15200H

Table 2-3: Default 16-bit segment and offset combinations.



Segment & Offset Addressing Scheme Allows Relocation

• This scheme allows both programs and data to be relocated in the memory (Figure 2-4).

• This also allows programs written to function in the real-mode to operate in a protected-mode system.

• Relocatable-program can be placed into any area of memory and executed without change.

• Relocatable-data can be placed in any area of memory and used without any change to the program.

Figure2-4: A memory system showing the placement of four memory segments

Table 2-2: Example of real mode segment addresses





Introduction to Protected Mode Memory Addressing

• Protected-mode memory addressing(80286) allows access to data & programs located → above first 1MB of memory & → within first 1MB of memory.

• In place of segment-address, segment-register contains a selector that selects a descriptor from a descriptor- table. (The extended memory system is accessed via a segment-address plus an offset-address, just as in the real mode. The difference is that the segment-address is not held in the segment-register. In the protected-mode, the segment starting-address is stored in a descriptor that is selected by the segment-register).

• Descriptor describes → memory-segment's location → length & → access rights

• Another difference in the 80386 is that the offset-address can be a 32-bit number instead of a 16-bit number.



Selectors & Descriptors

Selector(located in the segment-register) selects one of 8192 descriptors from one of 2 tables of descriptors.

Descriptor describes the location, length and access rights of the segment of memory.

• There are 2 descriptor-tables: 1) Global descriptor table & 2) Local descriptors table.

• Global-descriptors contain segment-definitions that apply to all programs whereas local-descriptors are usually unique to an application.

• Each descriptor-table contains 8192 descriptors, so a total of 16384 total descriptors are available to an application at any time.

• A descriptor contains 1) Base-address locates starting-address of memory-segment

2) Segment-limit contains last offset-address found in a segment (For example, if a segment begins at

memory location F00000H and ends at location F000FFH, the base-address is F00000H and the limit is FFH). 3) Access rights byte defines how the memory-segment is accessed via a program.

• For 80286 microprocessor, the base-address is a 24-bit address, so segments begin at any location in its 16MB of memory.

• In 80386, if G(granularity)=0, the limit specifies a segment-limit of 00000H to FFFFFH. If G=1, the value of the limit is multiplied by 4KB.

• In the 64-bit descriptor, if L=1, 64-bit address in a Pentium4 with 64-bit extensions is selected. if L=0, 32-bit compatibility mode is selected

• The AV bit is used by some operating-systems to indicate that the segment is available(AV=1) or not available(AV=0).

• D bit indicates how 80386 instructions access register & memory-data in protected- or real-mode. If D=0, the instructions are 16-bit instructions, compatible with the 8086 microprocessor. (This means that the instructions use 16-bit offset addresses and 16-bit register by default). If D=1, the instructions are 32-bit instructions.

Figure 2-6: The 80286 through Core2 64-bit descriptors



Figure 2-9: Using DS register to select a descriptor from the global descriptor table



Access Rights Byte

• This controls access to the protected-mode segment. This byte describes how the segment functions in the system.

• If the segment is a data-segment, the direction of growth is specified. If the segment grows beyond its limit, the operating-system program is interrupt to indicate a general protection-fault.

• The RPL(request privilege level) requests the access privilege-level of a memory-segment. If the RPL is higher than the privilege-level set by the access rights byte, access is granted. • The segment-register contains 3 fields of information:

→ Selector(First 13 bits) address one of 8192 descriptors from a descriptor-table. → TI bit selects either global descriptor-table(TI=0) or local descriptor-table(TI=1). → RPL(Last 2 bits) select the requested priority level for the memory segment access.

Figure 2-7:The access rights byte for the 80286 descriptor

Figure 2-8: The contents of a segment register during protected mode operation of the 80286 microprocessor



Program Invisible Registers

• These registers are not directly addressed by software so they are given this name.

• These registers control the microprocessor when operated in protected-mode.

• The program-invisible portion(cache-memory) of the segment-register is loaded with base-address, limit and access rights each time the number segment-register is changed.

• When a new segment-number is placed in a segment-register, the microprocessor accesses a descriptor-table and loads the descriptor into the program-invisible portion of the segment-register. It is held there and used to

access the memory-segment until the segment-number is again changed.

• The GDTR(global descriptor table register) & IDTR(interrupt descriptor table register) contain the base-address of the descriptor-table and its limit.(The limit of each descriptor-table is 16 bits because the maximum table length is 64KB)

• When the protected-mode operation is desired, the address of the global descriptor-table and its limit are loaded into the GDTR.

• The location of the local descriptor-table is selected from the global descriptor-table. One of the global descriptors is set up to address the local descriptor-table. To access the local descriptor-table, the LDTR(local descriptor table register) is loaded with a selector.

• This selector accesses the global descriptor-table and loads the address, limit and access rights of the local descriptor-table into the cache portion of the LDTR.

• The TR(task register) holds a selector, which accesses a descriptor that defines a task. (A task is most often a procedure or application program)

Figure 2-10:The program-invisible register within the 80286 microprocessor



Memory Paging

• Memory-paging mechanism allows any physical memory-location to be assigned to any linear-address.

• The linear-address is defined as the address generated by a program The physical-address is the actual memory-location accessed by a program.

Paging Registers

• Memory-paging is accomplished through control-registers CR0 and CR3.

• The paging-unit is controlled by the contents of the control-registers.

• The leftmost bit(PG) position of CR0 selects paging when placed at a logic 1 level. If PG bit is cleared(0), linear-address generated by program becomes physical-address used to access memory. If PG bit is set(1), linear-address is converted to a physical-address through paging-mechanism.

• The page directory base-address locates the directory for the page translation-unit.

• If PCD is set(1),the PCD pin becomes a logic one during bus cycles that are not paged.

• The page-directory contains upto 1024 entries that locate physical-address of a 4KB memory-page.

• The linear address is broken into 3 sections: 1) Page directory selects a page table that is indexed by the next 10 bits of the linear-address 2) Page table entry 3) Offset part selects a byte in the 4KB memory-page

• In 80486, the cache (translation look aside buffer-TLB) holds the 32 most recent page translation addresses.

Figure 2-11:The control register structure of the microprocessor

Figure 2-12: The format for the linear address



Flat Mode Memory

• In a Pentium-based computer, the memory-system that uses the 64-bit extensions uses a flat mode memory.

• A flat mode memory system is one in which there is no segmentation.

• The flat model does not use a segment-register to address a location in the memory.

• The CS segment-register is used to select a descriptor from the descriptor-table that defines the access rights of only a code-segment.

• The segment-register still selects the privilege-level of the software.

• The flat model does not select the memory-address of a segment using the base and limit in the descriptor.

• The flat mode memory contains 1TB of memory using a 40-bit address.

Figure 2-15: The 64-bit flat mode memory model




Data Addressing Modes

• MOV AX,BX;This instruction transfers the word contents of the source-register(BX) into the destination- register(AX).

• The source never changes, but the destination always changes.

• This instruction always copies the source-data into the destination.

• This instruction never actually picks up the data and moves it.

• Memory-to-memory transfers are not allowed by any instruction except for the MOVS instruction.

• The source & destination are called operands (ex: contents of AX, BX, LOC)

• An opcode(operation code) tells microprocessor which operation to perform(ex ADD, MOV, SUB).

Figure 3-1: The MOV instruction showing the source, destination and direction of data flow

Figure 3-2:8086 data addressing modes



Addressing Modes Register Addressing

• This transfers a copy of a byte(or word) from the source-register or contents of a memory-location to the destination-register or memory-location.

• Example: MOV CX, DX; This instruction copies word-sized contents of register DX into register CX. Immediate Addressing

• This transfers an immediate byte/word of source-data into the destination-register or memory-location.

• For example, MOV AL, 22H ;This instruction copies a byte-sized 22H into register AL. Direct Addressing

• This moves a byte(or word) between a memory-location and a register.

• For example, MOV CX, LIST ;This instruction copies the word-sized contents of memory-location LIST into register CX.

• Memory-to-memory transfers are not allowed by any instruction except for the MOVS instruction. Register Indirect Addressing

• This transfers a byte between a register and a memory-location addressed by base-register.

• The index & base registers are BP, BX, DI and SI.

• For example, MOV [BP], DL ;This instruction copies the byte-sized contents of register DL into the memory- location addressed by BP. Base Plus Index Addressing

• This transfers a byte between a register and the memory-location addressed by a base-register (BP or BX) plus an index-register (DI or SI).

• For example, MOV [BX+DI], CL ;this instruction copies the byte-sized contents of register CL into the memory- location addressed by BX plus DI. Register Relative Addressing

• This moves byte between a register and memory-location addressed by an index-or base-register plus a displacement.

• For example, MOV AX, [BX+4] ;This instruction loads AX from memory-location addressed by BX+4. Base-Relative-Plus Index Addressing

• This transfers a byte between a register and the memory-location addressed by a base- and an index-register plus a displacement.

• For example, MOV AX,[BX+DI+4] ;This instruction loads AX from memory-location addressed by BX+DI+4. Scaled Index Addressing

• The second register of a pair of registers is modified by the scale factor of 2*, 4* to generate the operand memory address.

• For example, MOV EDX, [EAX+4*EBX] ;This instruction loads EDX from memory-location addressed by EAX plus four times EBX.

• Scaling allows access to word(2*), doubleword(4*) memory array-data. RIP Relative Addressing

• This mode allows access to any location in the memory by adding a 32-bit displacement to the 64-bit contents of the 64-bit instruction pointer.



Register Addressing

• The microprocessor contains the following 8-bit registers used with register addressing: AH, AL, BH, BL, CH, CL, DH and DL.

• Also present are the following 16-bit registers: AX, BX, CX, DX, SP, BP, SI and DI.

• Some MOV instructions and the PUSH/POP instructions also use the 16-bit segment registers: CS, ES, DS, SS, FS and GS.

• Any instruction should use registers that are of same size {(AL,CL), (AX,CX)}. Never mix an 8-bit register with a 16-bit register because this is not allowed by the microprocessor and results in an error. A few instructions such as SHL DX, CL are exceptions to this rule.

• None of the MOV instructions affect the flag bits. The flag bits are normally modified by arithmetic or logic instructions (ADD, SUB, INC) • A segment-to-segment register MOV instruction is not allowed.

• The contents of the destination-register (or memory-location) change for all instructions except the CMP and TEST instructions.

Table 3-1: Examples of register-addressed instructions

Figure 3-3: The effect of executing the MOV BX,CX instruction at the point just before the BX register changes. Note that only

the rightmost 16bits of register EBX change

Example 3-1

MOV AX, BX ; copy contents of BX into AX

MOV CL, DH ; copy contents of DH into CL

MOV AX, CS ; copy CS into DS (2 steps)


MOV CS, AX ; copy AX into CS (causes problem)



Immediate Addressing

• The term ‘immediate’ implies that the data immediately follow the opcode in the memory.

• Immediate-data are constant-data, whereas data transferred from a register( or memory-location) are variable-data.

• This addressing operates upon a byte or word of data.

• MOV immediate instruction transfers a copy of immediate-data into a register or a memory-location.

• The symbolic assembler shows immediate-data in many ways. The letter H appends hexadecimal data. The letter B appends binary data.

Table 3-2: Examples of immediate addressing using the MOV instruction

Figure 3-4: Operation of the MOV EAX,13456H instruction. This instruction copies immediate data(13456) into EAX

Example 3-3

Label Opcode Operand Comment

DATA1 DB 23H ; defines DATA1 as a byte of 23H

DATA2 DW 1000H ;defines DATA2 as a word of 1000

START: MOV AL,BL ;copy BL into AL

MOV BH,AL ; copy AL into BH

MOV CX,200 ;copy 200 into CX

• Each statement in an assembly language program consists of 4 parts: 1) Label is used to store a symbolic-name for the memory-location that it represents. A label may be of

any length from 1 to 35 characters. 2) Opcode-field is used to hold the instruction or opcode 3) Operand-field contains information used by the opcode

4) Comment-field contains a comment about an instruction or a group of instructions. A comment always begins with a semicolon (;)

Example 3-2:

.MODEL TINY ; choose single segment model

.CODE ; start of code segment

.STARTUP ; start of program MOV AX,0 ;place 0000H into AX MOV SI,AX ;copy AX into SI .EXIT ;exit to DOS END ;end of program

• .MODEL TINY directs the assembler to assemble the program into a single code segment.

• .CODE indicates the start of the code segment

• .STARTUP indicates the start of the code.

• .EXIT causes the program to exit to DOS.

• .END indicates the end of the program file.



Example 3-6 .MODEL SMALL ; choose small model .DATA ; start data segment

DATA1 DB 10H ; place 10H into DATA1 DATA2 DB 2H ; place 02H into DATA2 DATA3 DW 0 ; place 0000H into DATA3 DATA4 DW 1234H ; place 1234H into DATA4 .CODE ; start code segment

.STARTUP ; start program

MOV AL,DATA1 ; copy DATA1 into AL MOV AH,DATA2 ; copy DATA2 into AH MOV DATA3,AX ; copy AX into DATA3 MOV BX,DATA4 ; copy DATA4 into BX .EXIT ; exit to DOS

END ; end program listing

• .DATA is used to inform the assembler where the data segment begins.

• .SMALL model allows one data segment and one code segment. A SMALL model program assembles as an execute(.EXE) program file.

• .STARTUP -indicates the start of the code & -loads the DS register with the segment address of the data segment memory

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