Working & Construction of Analog and Digital Converters, Study notes for Electronic Measurement and Instrumentation. Agra University
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Working & Construction of Analog and Digital Converters, Study notes for Electronic Measurement and Instrumentation. Agra University

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Converters

CHAPTER 6: CONVERTERS INTRODUCTION 6.1 SECTION 6.1: DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES 6.3 DIGITAL-TO ANALOG CONVERTERS (DACs OR D/As) INTRODUCTION 6.3 KELVIN DIVIDER (STRING DACs) 6.4 SEGMENTED DACs 6.5 DIGITAL POTS 6.7 THERMOMETER (FULLY DECODED) DACs 6.9 BINARY WEIGHTED CURRENT SOURCES 6.12 R-2R LADDER 6.14 MULTIPLING DACs 6.18 SEGMENTED DACs 6.20 SIGMA-DELTA DACs 6.22 I/V CONVERTERS 6.23 DIFFERENTIAL TO SINGLE-ENDED CONVERSION TECHNIQUES 6.24 SINGLE-ENDED CURRENT-TO-VOLTAGE CONVERSION 6.27 DIFFERENTIAL CURRENT-TO-VOLTAGE CONVERSION 6.27 DIGITAL INTERFACES 6.28 DATA CONVERTER LOGIC: TIMING AND OTHER ISSUES 6.33 INTERPOLATING DACs (INTERPOLATING TxDACs) 6.33 RECONSTRUCTION FILTERS 6.35 SIN(X)/(X) (SINC) 6.36 INTENTIONALLY NONLINEAR DACs 6.37 SECTION 6.2: ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES 6.40 THE COMPARATOR: A 1-BIT ADC 6.44 SUCCESSIVE APPROXIMATION ADCs 6.45 FLASH CONVERTERS 6.50 SUBRANGING, ERROR CORRECTED, AND PIPELINED ADCs 6.52 SERIAL BIT-PER-STAGE BINARY AND GRAY CODED (FOLDING) ADCs 6.58 COUNTING AND INTEGRATING ADC ARCHITECTURES 6.64 CHARGE RUN-DOWN ADCs 6.65 RAMP RUN-UP ADCs 6.65 TRACKING ADCs 6.66 VOLTAGE-TO-FREQUENCY CONVERTERS (VFCs) 6.68 DUAL-SLOPE/MULTISLOPE ADCs 6.73 RESOLVER-TO-DIGITAL CONVERTERS (RDCs) AND SYNCHROS 6.76

BASIC LINEAR DESIGN

SECTION 6.2: ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES (cont.) REFERENCES 6.80 SECTION 6.3: SIGMA-DELTA (ΣΔ) CONVERTERS 6.85 HISTORICAL PERSPECTIVE 6.85 BASICS OF SIGMA-DELTA ADCs 6.90 IDLE TONE CONSIDERATIONS 6.96 HIGHER ORDER LOOP CONSIDERATIONS 6.98 MULTIBIT SIGMA-DELTA CONVERTERS 6.98 DIGITAL FILTER IMPLICATIONS 6.100 HIGH RESOLUTION MEASUREMENT SIGMA-DELTA ADCs 6.102 BAND-PASS SIGMA-DELTA CONVERTERS 6.107 SIGMA-DELTA DACs 6.108 SUMMARY 6.110 REFERENCES 6.111 SECTION 6.4: DEFINING THE SPECIFICATIONS 6.115 SECTION 6.5: DAC AND ADC STATIC TRANSFER FUNCTIONS AND DC ERRORS 6.117 SECTION 6.6: DATA CONVERTER AC ERRORS 6.129 NOISE IN PRACTICAL ADCs 6.131 EQUIVALENT INPUT REFERRED NOISE 6.131 NOISE-FREE (FLICKER-FREE) CODE RESOLUTION 6.132 DYNAMIC PERFORMANCE OF DATA CONVERTERS 6.133 INTEGRAL AND DIFFERENTIAL NONLINEARITY DISTORTION EFFECTS 6.133 HARMONIC DISTORTION, WORST HARMONIC, TOTAL HARMONIC DISTORTION (THD), TOTAL HARMONIC DISTORTION PLUS NOISE (THD + N) 6.135 SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD), SIGNAL-TO-NOISE RATIO (SNR) AND EFFECTIVE NUMBER OF BITS (ENOB) 6.136 ANALOG BANDWIDTH 6.137 SPURIOUS-FREE DYNAMIC RANGE (SFDR) 6.138 TWO TONE INTERMODULATION DISTORTION (IMD) 6.141 MULTITONE SPURIOUS-FREE DYNAMIC RANGE 6.142 SECOND- AND THIRD-ORDER INTERCEPT POINTS, 1 dB COMPRESSION POINT 6.143 WIDEBAND CDMA (W-CDMA) ADJACENT CHANNEL POWER RATIO (ACPR) AND ADJACENT CHANNEL LEAKAGE RATIO (ADLR) 6.145 NOISE POWER RATIO (NPR) 6.146 NOISE FACTOR (F) AND NOISE FIGURE (NF) 6.149

Converters

SECTION 6.6: DATA CONVERTER AC ERRORS (cont.) APERTURE TIME, APERTURE DELAY TIME, AND APERTURE JITTER 6.156 A SIMPLE EQUATION FOR THE TOTAL SNR OF AN ADC 6.160 ADC TRANSIENT RESPONSE AND OVERVOLTAGE RECOVERY 6.161

ADC SPARKLE CODES, METASTABLE STATES, AND BIT ERROR RATE (BER) 6.163

DAC DYNAMIC PERFORMANCE 6.167 DAC SETTLING TIME 6.167 GLITCH IMPULSE AREA 6.168 DAC SFDR AND SNR 6.170 MEASURING DAC SNR WITH AN ANALOG SPECTRUM ANALYZER 6.172 OTHER AC SPECIFICATIONS 6.173 REFERENCES 6.175 SECTION 6.7: TIMING SPECIFICATIONS 6.177 SECTION 6.8: HOW TO READ A DATA SHEET 6.181 THE FRONT PAGE 6.181 THE SPECIFICATION TABLES 6.181 THE ABSOLUTE MAXIMUMS 6.188 THE ORDERING GUIDE 6.189 PIN DESCRIPTION 6.191 DEFINING THE SPECIFICATIONS 6.192 EQUIVALENT CIRCUITS 6.193 THE GRAPHS 6.194 THE MAIN BODY 6.198 CIRCUIT DESCRIPTION 6.198 INTERFACE 6.199 REGISTER DESCRIPTION 6.201 APPLICATIONS CIRCUITS 6.202 EVALUATION BOARDS 6.203 SUMMARY 6.203 SECTION 6.9: CHOOSING A DATA CONVERTER 6.205 DETERMINE THE PARAMETERS 6.205 PRIORITIZING THE PARAMETERS 6.206 SELECTING THE PART 6.206

BASIC LINEAR DESIGN

CONVERTERS INTRODUCTION

6.1

CHAPTER 6: CONVERTERS Introduction There are two basic type of converters, digital-to-analog (DACs or D/As) and analog-to- digital (ADCs or A/Ds). Their purpose is fairly straightforward. In the case of DACs, they output an analog voltage that is a proportion of a reference voltage, the proportion based on the digital word applied. In the case of the ADC, a digital representation of the analog voltage that is applied to the ADCs input is outputted, the representation proportional to a reference voltage. In both cases the digital word is almost always based on a binarily weighted proportion. The digital input or output is arranged in words of varying widths, referred to as bits, typically anywhere from 6 bits to 24 bits. In a binarily weighted system each bit is worth half of the bit to its left and twice the bit to its right. The greater the number of bits in the digital word, the finer the resolution. These bits are typically arranged in groups of four, called bytes, for convenience. For a better understanding of the relationship between the digital domain and the analog domain please refer to the section on sampling theory. As stated earlier, we shall look at the operation of converters primarily from a “black box” view. We will concern ourselves less with the internal construction of the converter and more with its operation. We cannot, however, completely ignore the internal architecture because in many cases it is relevant to operational advantages or limitations. There are a number of works that cover the internal workings of the converters in much more detail (see References). Another point that should be kept in mind is the difference between accuracy and resolution. The resolution of a converter is the number of bits in its digital word. The accuracy is the number of those bits that meet the specifications. For instance, a DAC might have 16 bits of resolution, but might only be monotonic to 14 bits. This means that the assured accuracy of the DAC will be no better than 14 bits. Also, an audio ADC might have a digital word width of 16 bits, but the SNR may be only 70 dB. This means that the accuracy will only be at the 12-bit level. This is not to say that the other bits are irrelevant. With further processing, typically filtering, often the accuracy can be improved. While these terms are similar and sometimes used interchangeably, the distinction between the two should be remembered. We shall examine the DAC first.

BASIC LINEAR DESIGN

6.2

CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

6.3

SECTION 6.1: DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES Digital-to-Analog Converters (DACs or D/As) Introduction What we commonly refer to as a DAC today is typically quite a bit more. The DAC will typically have the converter itself and a collection of support circuitry built into the chip. The first DACs were board level designs, built from discrete components, including vacuum tubes as the switching elements. Monolithic DACs began to appear in the early ’70s. These early examples were actually sub-blocks of the DAC. An example of this would be the AD550, which was a 4 bit binarily weighted current source. This current source block would be mated to a separate part, such as the AD850, which contained a resistor array and CMOS switches. Together these would form the basic DAC. As we moved on in time these functions were integrated on the same die, additional digital circuitry, specifically latches to store the digital input, were added. Then a second rank of latches was often added. The purpose of the second rank was to allow the microprocessor or microcontroller to write to many DACs in a system and the updated them all at the same time. The input rank of latches could also be a shift register, which would allow a serial interface.

Figure 6.1: The Basic DAC

DIGITAL INPUT

VDD

VSS GROUND (MAY BE INTERNALLY CONNECTED TO VSS)

(ANALOG) REFERENCE

INPUT

DAC

VREF

BASIC LINEAR DESIGN

6.4

On the back end, since the output of the DAC is often a current, an op amp is often added to perform the current-to-voltage (I/V) conversion. On the front end a voltage reference is often added. Process limitations did not allow the integration of all these sub-blocks to occur at once. Initially, the processes used to make the various sub-blocks were not compatible. The process that made the best switches was typically not the best for the amplifier and the reference. As the processes became more advanced these limitations became less. Today CMOS can make acceptable amplifiers and processes combining bipolar and CMOS together exist. There are several advantages to including all this additional circuitry in one package. The first is the obvious advantage of reducing the chip count. This reduces the size of the circuitry and increases the reliability. Probably more important is that the circuit designer now doesn’t have to concern himself with the accuracy of several parts in a system. The system is now one part and tested by the manufacturer as a unit. Next we will look at the various DAC architectures. When we refer to DACs here we are referring to the basic converter rather than the complete system. Kelvin Divider (String DAC) The simplest structure of all is the Kelvin divider or string DAC as shown in Figure 6.2. An N-bit version of this DAC simply consists of 2N equal resistors in series and 2N switches (usually CMOS), one between each node of the chain and the output. The output is taken from the appropriate tap by closing just one of the switches (there is some slight digital complexity involved in decoding to 1 of 2N switches from N-bit data). This architecture is simple, has a voltage output and is inherently monotonic—even if a resistor is accidentally short-circuited, output n cannot exceed output n + 1. It is linear if all the resistors are equal, but may be made deliberately nonlinear if a nonlinear DAC is required. The output is a voltage, but it has the disadvantage of having a relatively large output impedance. This output impedance is also code dependant (the impedance changes with changes to the digital input). In many cases it will be beneficial to follow the output of the DAC with an op amp to buffer this output impedance and present a low impedance source to the following circuitry. Since only two switches operate during a transition it is a low glitch architecture (the concept of glitch will be examined in a following section). Also, the switching glitch is not code-dependent, making it ideal for low distortion applications. Because the glitch is constant regardless of the code transition, the frequency content of the glitch is at the DAC update rate and its harmonics—not at the harmonics of the DAC output signal frequency. The major drawback of the Kelvin DAC is the large number of resistors and switches required for high resolution. There are 2N resistors required, so a 10 bit DAC would require 1024 switches and resistors, and as a result it was not commonly used as a simple DAC architecture until the recent advent of very small IC feature sizes made it very practical for low and medium resolution (typically up to 10 bits) DACs.

CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

6.5

Figure 6.2: Simplest Voltage-Output Thermometer DAC:The Kelvin Divider

As we mentioned in the section on sampling theory, the output of a DAC for an all 1s code is 1 LSB below the reference, so a Kelvin divider DAC intended for use as a general-purpose DAC has a resistor between the reference terminal and the first switch as shown in Figure 6.2. Segmented String DACs A variation of the Kelvin divider is the segmented string DAC. Here we reduce the number of resistors required by segmenting. Figure 6.3 shows two varieties of segmented voltage-output DAC. The architecture in Figure 6.3A is sometimes called a Kelvin- Varley Divider. Since there are buffers between the first and second stages, the second string DAC does not load the first, and the resistors in the second string do not need to have the same value as the resistors in the first. All the resistors in each string, however, do need to be equal to each other or the DAC will not be linear. The examples shown have 3-bit first and second stages but for the sake of generality, let us refer to the first (MSB) stage resolution as M-bits and the second (LSB) as K-bits for a total of N = M + K bits. The MSB DAC has a string of 2M equal resistors and a string of 2K equal resistors in the LSB DAC. As an example, if we make a 10-bit string DAC out of two 5-bit sections, each segment would have 25 or 32 resistors, for a total of 64, as opposed to the 1024 required for a standard Kelvin divider. This is an obvious advantage.

3-TO-8 DECODER

3-BIT DIGITAL INPUT

ANALOG OUTPUT

VREF

CIRCA 1920

SWITCHES WERE RELAYS OR VACUUM TUBES

8

TO SWITCHES

R

R

R

R

R

R

R

R

BASIC LINEAR DESIGN

6.6

Figure 6.3: Segmented Voltage-Output DACs

Buffer amplifiers can have offset, of course, and this can cause nonmonotonicity in a buffered segmented string DAC. In the simpler configuration of a buffered Kelvin-Varley divider buffer (Figure 6.3A), buffer A is always “below” (at a lower potential than) buffer B, and the extra tap labeled “A” on the LSB string DAC is not necessary. The data decoding is just two priority encoders. But if the decoding of the MSB string DAC is made more complex so that buffer A can only be connected to the taps labeled “A” in the MSB string DAC, and buffer B to the taps labeled “B,” then it is not possible for buffer offsets to cause nonmonotonicity. Of course, the LSB string DAC decoding must change direction each time one buffer “leapfrogs” the other, and taps A and B on the LSB string DAC are alternately not used—but this involves a fairly trivial increase in logic complexity and is justified by the increased performance. Rather than using a second string of resistors, a binary R-2R DAC can be used to generate the three LSBs as shown in Figure 6.3B. This voltage-output DAC (Figure 6.3B) consists of a 3-bit string DAC followed by a 3-bit buffered voltage-mode ladder network. Again the number of resistors require for the DAC is reduced. An unbuffered version of the segmented string DAC is shown in Figure 6.4. This version is more clever in concept. Here, the resistors in the two strings must be equal, except that the top resistor in the MSB string must be smaller—1/2K of the value of the others—and the LSB string has 2K – 1 resistors rather than 2K. Because there are no buffers, the LSB string appears in parallel with the resistor in the MSB string that it is switched across and loads it. This drops the voltage across that MSB resistor by 1 LSB of the LSB DAC— which is exactly what is required. The output impedance of this DAC, being unbuffered,

KELVIN-VARLEY DIVIDER ("STRING DAC")

VREF VREF

OUTPUT

KELVIN DIVIDER AND R-2R LADDER NETWORK

NOTE: MSB OF LADDER

ON RIGHT

IF THE LADDER NETWORK IS MONOTONIC, THE

WHOLE DAC IS MONOTONIC

OUTPUT

(A) (B)

A

B

A

B

A

B

A

B

A

A

B A

B

CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

6.7

varies with changing digital code. This circuit is intrinsically monotonic since it is unbuffered (and, of course, can be manufactured on CMOS processes which make resistors and switches but not high precision amplifiers, so it may be cheaper as well).

Figure 6.4: Segmented Unbuffered String DACs Use Patented Architecture In order to understand this clever concept better, the actual voltages at each of the taps has been worked out and labeled for the 6-bit segmented DAC composed of two 3-bit string DACs shown in Figure 6.4. The reader is urged to go through this simple analysis with the second string DAC connected across any other resistor in the first string DAC and verify the numbers. A detailed mathematical analysis of the unbuffered segmented string DAC can be found in the relevant patent filed by Dennis Dempsey and Christopher Gorman of Analog Devices in 1997 (Reference 14). Digital Potentiometers Another variation of the string DAC is the digital potentiometer. A simple digital potentiometer is shown in Figure 6.5. The major difference is that the lower arm of the potentiometer (terminal B) is not connected to ground, but is instead left floating. The absolute values of the resistors in a Kelvin DAC typically are not critical. They are limited by the available material. They must, of course, be the same as each other. In a digital potentiometer the end-to-end resistance is specified. The accuracy of the end to end resistance is on the order of a

R

R

R

R

R

R

R

R

R 8

VREF

63 64

VREF

55 64

VREF

54 64

VREF

53 64

VREF

52 64

VREF 51 64

VREF

50 64

VREF

49 64

VREF

48 64

VREF

40 64

VREF

32 64

VREF 24 64

VREF 16 64

VREF

8 64

VREF

OUTPUT

R

R

R

R

R

R

R

55 64

VREF

48 64

VREF

Dennis Dempsey and Christopher Gorman, "Digital-to-Analog Converter," U.S. Patent 5,969,657, filed July 27, 1997, issued October 19, 1999.

BASIC LINEAR DESIGN

6.8

mechanical potentiometer. Digital potentiometers are typically available in end-to-end resistance values from 10 kΩ to 1 MΩ. Lower values of end-to-end resistance are difficult since the on resistance of the CMOS switches is on the order of the resistor segment, so the linearity of the pot suffers at the low end.

Figure 6.5: A Slight Modification to a Kelvin DAC Yields a "Digital Potentiometer" The advantages to digital potentiometers are many. Even the lowest resolution digital potentiometers have better setability than their mechanical counterparts. Also, they are immune to mechanical vibration and oxidation of the wiper contact. Obviously, adjustments can be made without human intervention. In most digital potentiometers the voltage on the input pins can not exceed the supplies (typically 3 V or 5 V) due to the CMOS switches used in their construction, but certain models are designed for ±15 V operation. Another design feature on many of the digital potentiometers is that on power up (sometimes from an internal timer, sometimes controlled by an external pin) the wiper is shorted to one of the terminals. This is useful since output on power up is undefined until it is written to. Since it might take a while (relatively) for the micro-controller to initialize itself and then get around to initializing the rest of the system, having the digital potentiometer in a known state can be useful. Some digital potentiometers incorporate nonvolatile logic so that their settings are retained when they are turned off. One time programmable (OTP) versions of digital potentiometers have become available. Here the digital code is locked into the potentiometer once the setting had been determined. The technology used is fuseable links. A variation on this theme is the two

3-TO-8 DECODER

3-BIT DIGITAL INPUT

TAP

8

TO SWITCHES

R

R

R

R

R

R

R

TERMINAL A

TERMINAL B

CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

6.9

times programeable (TTP) digital potentiometer. This allows the nonvolatile settings to be modified one time. The block diagram of a TTP digital potentiometer is shown in Figure 6.6.

Figure 6.6: Two Times Programmable (TTP) Digital Potentiometer Block Diagram

Thermometer (Fully Decoded) DACs There is a current-output DAC architecture analogous to a string DAC which consists of 2N – 1 switchable current sources (which may be resistors and a voltage reference or may be active current sources) connected to an output terminal. This output must be at, or close to, ground. Figure 6.7 shows a thermometer DAC which use resistors connected to a reference voltage to generate the currents. If active current sources are used as shown in Figure 6.8, the output may have more compliance (the allowable voltage on the output pin which still guarantees performance), and a resistive load is typically used to develop an output voltage. The load resistor must be chosen so that at maximum output current the output terminal remains within its rated compliance voltage Once a current in a thermometer DAC is switched into the circuit by increasing the digital code, any further increases do not switch it out again. The structure is thus inherently monotonic, irrespective of inaccuracies in the currents. Again, like the Kelvin divider, only the advent of high density IC processes has made this architecture practical for general purpose medium resolution DACs, although a slightly more complex version—shown in the next diagram—is quite widely used in high speed applications. Unlike the Kelvin divider, this type of current-mode DAC does not have a unique name, although both types may be referred to as fully decoded DACs or thermometer DACs.

VDD

GND

SDA

SCL

AD0

AD1

W

RDAC REGISTER

ADDRESS DECODE

SERIAL INPUT REGISTER

BA

FUSE LINKS

1 2

/ 8

BASIC LINEAR DESIGN

6.10

Figure 6.7: The Simplest Current-Output Thermometer (Fully Decoded) DAC

A DAC where the currents are switched between two output lines—one of which is often grounded, but may, in the more general case, be used as the inverted output—is more suitable for high speed applications because switching a current between two outputs is far less disruptive, and so causes a far lower glitch than simply switching a current on and off. This architecture is shown in Figure 6.9.

Figure 6.8: Current Sources Improve the Basic

Current-Output Thermometer DAC

3-BIT DIGITAL INPUT

CURRENT OUTPUT INTO

VIRTUAL GROUND

(USUALLY AN OP-AMP I-V

CONVERTER)

VREF

3-TO-7 DECODER

R R R R R R R

TO SWITCHES

7

3-BIT DIGITAL INPUT

3-TO-7 DECODER

I I I I I I I

CURRENT OUTPUT

MAY HAVE COMPLIANCE OF 1 OR 2 V

TO SWITCHES

7

CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

6.11

Figure 6.9: High Speed Thermometer DAC with

Complementary Current Outputs But the settling time of this DAC still varies with initial and final code, giving rise to intersymbol distortion (ISI). This can be addressed with even more complex switching where the output current is returned to zero before going to its next value. Note that although the current in the output is returned to zero it is not “turned off”—the current is dumped to ground when it is not being used, rather than being switched on and off. The techniques involved are too complex to discuss in detail here but can be found in the references. In the normal (linear) version of this DAC, all the currents are nominally equal. Where it is used for high speed reconstruction, its linearity can also be improved by dynamically changing the order in which the currents are switched by ascending code. Instead of code 001 always turning on current A; code 010 always turning on currents A and B, code 011 always turning on currents A, B, and C; etc. the order of turn-on relative to ascending code changes for each new data point. This can be done quite easily with a little extra logic in the decoder. The simplest way of achieving it is with a counter which increments with each clock cycle so that the order advances: ABCDEFG, BCDEFGA, CDEFGAB, etc., but this algorithm may give rise to spurious tones in the DAC output. A better approach is to set a new pseudo-random order on each clock cycle—this requires a little more logic, but even complex logic is now very cheap and easily implemented on CMOS processes. There are other, even more complex, techniques which involve using the data itself to select bits and thus turn current mismatch into shaped noise. Again they are too complex for a book of this sort. (See references for a more detailed discussion).

3-BIT DIGITAL INPUT

3-TO-7 DECODER

I I I I I I I

CURRENT OUTPUTS MAY HAVE

COMPLIANCE OF 1 OR 2 V

OUTPUT OUTPUT

A B C D E F G

TO SWITCHES

7

BASIC LINEAR DESIGN

6.12

Binary Weighted Current Source The voltage-mode binary-weighted resistor DAC shown in Figure 6.10 is usually the simplest textbook example of a DAC. However, this DAC is not inherently monotonic and is actually quite hard to manufacture successfully at high resolutions due to the large spread in component (resistor) values. In addition, the output impedance of the voltage- mode binary DAC changes with the input code.

Figure 6.10: Voltage-Mode Binary-Weighted Resistor DAC

Current-mode binary weighted DACs are shown in Figure 6.11A (resistor-based), and Figure 6.11B (current-source based). An N-bit DAC of this type consists of N weighted current sources (which may simply be resistors and a voltage reference) in the ratio 1:2:4:8:....:2N–1. The LSB switches the 2N–1 current, the MSB the 1 current, etc. The theory is simple but the practical problems of manufacturing an IC of an economical size with current or resistor ratios of even 128:1 for an 8-bit DAC are enormous, especially as they must have matched temperature coefficients. This architecture is virtually never used on its own in integrated circuit DACs, although, again, 3-bit or 4-bit versions have been used as components in more complex structures. For example, the AD550 mentioned at the beginning of this section is an example of a binary-weighted DAC. If the MSB current is slightly low in value, it will be less than the sum of all the other bit currents, and the DAC will not be monotonic (the differential nonlinearity of most types of DAC is worst at major bit transitions). However, there is another binary-weighted DAC structure which has recently become widely used. This uses binary-weighted capacitors as shown in Figure 6.12. The problem with a DAC using capacitors is that leakage causes it to lose its accuracy within a few milliseconds of being set. This may make capacitive DACs unsuitable for general- purpose DAC applications, but it is not a problem in successive approximation ADCs,

R/8 R/4 R/2 R

V

V

REF

OUT

MSBLSB

Adapted from: B. D. Smith, "Coding by Feedback Methods," Proceedings of the I. R. E., Vol. 41, August 1953, pp. 1053-1058

CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

6.13

since the conversion is complete in a few µs or less—long before leakage has any appreciable effect.

DIFFICULT TO FABRICATE IN IC FORM DUE TO LARGE RESISTOR OR CURRENT RATIOS FOR HIGH RESOLUTIONS

VREF

MSB LSB

R 2R 4R 8R

MSB LSB

I I 2

I 4

I 8

CURR ENT OUTPUTS INTO VIRTUAL GROUNDS

(A) RESISTOR (B) CURR ENT SOURCE

Figure 6.11: Current-Mode Binary-Weighted DACs

Figure 6.12: Capacitive Binary-Weighted DAC in

Successive Approximation ADC The use of capacitive charge redistribution DACs offers another advantage as well—the DAC itself behaves as a sample-and-hold circuit (SHA), so not only is an external SHA

_

+ C/ 4C/ 2C C/ 4

AIN

VREF

SIN

SC

S1 S2 S3 S4

BIT1 (MSB)

BIT2 BIT3 (LSB)

SWITCHES SHOWN IN TRACK (SAMPLE) MODE

A

CTOTAL = 2C

BASIC LINEAR DESIGN

6.14

unnecessary with these ADCs, there is no need to allocate separate chip area for a separate integral SHA. R-2R Ladder One of the most common DAC building-block structures is the R-2R resistor ladder network shown in Figure 3.15. It uses resistors of only two different values, and their ratio is 2:1. An N-bit DAC requires 2N resistors, and they are quite easily trimmed. There are also relatively few resistors to trim.

Figure 6.13: 4-Bit R-2R Ladder Network This structure is the basis of a large family of DACs. Figure 6.14 is the block diagram of the AD7524, which is typical of a basic current output CMOS DAC. The diagram shows the structure of the DAC.

Figure 6.14: AD7524 CMOS DAC Block Diagram

2R 2R 2R 2R 2R

R R R

AD7524

DATA LATCHES

CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

6.15

The input impedance (basically the value of the resistors) is not a closely specified parameter. The specified range is 4:1 (5 kΩ min, 20 kΩ max, although it is typically closer than that). It is the relative accuracy, not the absolute accuracy of the resistors that is of interest. In most applications the absolute value is not important. Certain applications exist where the value does matter. In these instances, the parts must be selected at test. Note the extra resistor added at the RFEEDBACK pin. This is designed to be the feedback resistor for the I/V op amp. This resistor is trimmed along with the rest of the resistors so it tracks. Also, since it is made of the same material as the rest of the resistors, therefore having the same temperature coefficient, and is on the same substrate, hence at the same temperature, it will track over temperature. Figure 6.15 shows a more modern example of a CMOS DAC, the AD7394. Several trends are obvious here. First off, the output is voltage, not current. Advancements in process technology have allowed reasonable quality CMOS op amps to be created. Also note the two ranks of latches. The purpose of these latches is to allow the micro- controller to write to all converters in a system and then update them all at the same time. This will be covered on more detail in a later section. Note also the power on reset circuit. Since the wake up state of a CMOS DAC is undefined and not repeatable, many modern DACs include a circuit to force the output to either half scale of minimum scale, depending on whether the intended application is unipolar or bipolar. Probably the most obvious difference is that this is a multiple DAC package. Shrinking device geometries have allowed more circuitry to be included, even with the smaller packages in use today.

Figure 6.15: AD7394 Quad CMOS DAC Block Diagram

BASIC LINEAR DESIGN

6.16

The previous examples were CMOS devices, that is to say, that the switches were implemented with CMOS switches. The switches could also be implemented with bipolar transistors (BJT). An example of this is the classic DAC-08. Its block diagram is shown in Figure 6.16. One major difference in the BJT implementation is that the switch allows current in one direction, versus the CMOS switch, which can allow bidirectional current. This limits the BJT DAC to 2-quadrant operation while the CMOS version can be 4-quadrant. Supplies tend to be different as well.

Figure 6.16: DAC-08 Block Diagram

There are two ways in which the R-2R ladder network may be used as a DAC—known respectively as the voltage mode and the current mode (they are sometimes called “normal” mode and “inverted” mode, but as there is no consensus on whether the voltage mode or the current mode is the “normal” mode for a ladder network this nomenclature can be misleading, although in most cases the current mode would be considered the “normal” mode). Each mode has its advantages and disadvantages. In the current-mode R-2R ladder DAC shown in Figure 6.17, the gain of the DAC may be adjusted with a series resistor at the VREF terminal, since in the current mode, the end of the ladder, with its code-independent impedance, is used as the VREF terminal; and the ends of the arms are switched between ground and an output line which must be held at ground potential. The normal connection of a current-mode ladder network output is to an op amp’s inverting input (virtual ground), but stabilization of this op amp is complicated by the DAC output impedance variation with digital code.

VREF (+) 14

15

V+ VLC MSB

B1 B2 B3 B4 B5 B6 B7 (LSB)

B8

13 1 5 6 7 8 9 10 11 12

V–COMP

316

4 2

IOUT

IOUT

BIAS NETWORK

CURRENT SWITCHES

VREF (–)

REFERENCE AMPLIFIER

DAC08

CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

6.17

Figure 6.17: Current-Mode R-2R Ladder Network DAC

Current-mode operation has a larger switching glitch than voltage mode since the switches connect directly to the output line(s). However, since the switches of a current- mode ladder network are always at ground potential, their design is less demanding and, in particular, their voltage rating does not affect the reference voltage rating. If switches capable of carrying current in either direction (such as CMOS devices) are used, the reference voltage may have either polarity, or may even be ac. Such a structure is one of the most common types used as a multiplying DAC (MDAC) which will be discussed later in this section. Since the switches are always at, or very close to, ground potential, the maximum reference voltage may greatly exceed the logic voltage, provided the switches are make- before-break—which they are in this type of DAC. It is not unknown for a CMOS MDAC to accept a ±30 V reference (or even a 60-V peak-to-peak ac reference) while working from a single 5 V supply. In the voltage mode R-2R ladder DAC shown in Figure 6.18, the “rungs” or arms of the ladder are switched between VREF and ground, and the output is taken from the end of the ladder. The output may be taken as a voltage, but the output impedance is independent of code, so it may equally well be taken as a current into a virtual ground. The voltage output is an advantage of this mode, as is the constant output impedance, which eases the stabilization of any amplifier connected to the output node. Additionally, the switches switch the arms of the ladder between a low impedance VREF connection and ground, which is also, of course, low impedance, so capacitive glitch currents tend not to flow in the load. On the other hand, the switches must operate over a wide voltage range (VREF to ground), which is difficult from a design and manufacturing viewpoint, and the reference input impedance varies widely with code, so that the reference input must be driven from a very low impedance. In addition, the gain of the DAC cannot be adjusted by means of a resistor in series with the VREF terminal.

2R

RRR

2R2R2R2R

VREF

MSB LSB

CURRENT OUTPUT

INTO VIRTUAL GROUND

<< R

*

* GAIN TRIM IF REQUIRED

BASIC LINEAR DESIGN

6.18

Figure 6.18: Voltage-Mode R-2R Ladder Network DAC

Probably the most important advantage to the voltage mode is that it allows single-supply operation. This is because the op amp that is commonly used as I/V converter in the current mode converter is in the inverting configuration so would require a negative output for a positive input, assuming ground reference. Of course you could bias everything up to a rail-splitter ground, but that introduces other issues into the system. Multiplying DACs (MDACs) In most cases the reference to a DAC is a highly stable dc voltage. In some instances, however, it is useful to have a variable reference. The R-2R ladder structure using CMOS switches can easily handle a bipolar signal on its input. Having the ability to have bipolar (positive and negative) signals on the input allows construction of 2-quadrant and 4-quadrant Multiplying DACs. Figure 6.19 shows the schematic and Table I outlines the operation of a 2-quadrant MDAC and Figure 6.20 shows the schematic and Table II outlines the operation of a 4-quadrant MDAC for an 8-bit DAC. DACs utilizing bipolar transistors as switches, such as the DAC-08 above, cannot accommodate bipolar signals on the reference. Therefore they can only implement 2-quadrant MDACs. In addition, the reference voltage can not go all the way to 0 V. The maximum allowable range is typically from 10% to 100% of the allowable reference voltage range. One of the main applications of the MDAC is as a variable gain amplifier, where the gain is controlled by the digital word applied to the MDAC.

2R

R R R

2R 2R 2R 2R

V

V

REF

OUT

MSBLSB

Adapted from: B. D. Smith, "Coding by Feedback Methods," Proceedings of the I. R. E., Vol. 41, August 1953, pp. 1053-1058

CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

6.19

Figure 6.19: 2-Quadrant Multiplying DAC

Figure 6.20: 4-Quadrant Multiplying DAC

BASIC LINEAR DESIGN

6.20

The frequency response of the MDAC is limited by the parasitic capacitance across the switches in the off condition. As the frequency goes up the impedance of the capacitors goes down, effectively bypassing the switch. This reduces the off isolation at higher frequencies. Typically the frequency response of an MDAC will be on the order of 1 MHz.

Segmented DACs So far we have considered mostly basic DAC architectures. When we are required to design a DAC with a specific performance, it may well be that no single architecture is ideal. In such cases, two or more DACs may be combined in a single higher resolution DAC to give the required performance. These DACs may be of the same type or of different types and need not each have the same resolution. For example, the segmented string DAC is a segmented DAC where 2 Kelvin DACs are cascaded. Typically, one DAC handles the MSBs, another handles the LSBs, and their outputs are added in some way. The process is known as “segmentation,” and these more complex structures are called “segmented DACs.” There are many different types of segmented DACs and some, but by no means all, will be illustrated in the next few diagrams. It is sometimes not obvious from looking at the data sheet that a particular DAC is segmented.

Figure 6.21: Segmented Current-Output DACs: (A) Resistor-Based, (B) Current-Source Based

Very high speed DACs for video, communications, and other HF reconstruction applications are often built with arrays of fully decoded current sources. The two or three

R R R R R R R 2R2R 2R 2R 2R

R R R VREF

-3-BIT MSB THERMOMETER DAC 4-BIT R-2R DAC

CURRENT OUTPUT

CURRENT

I I I I I I I I 4

I 2

I 8

I 16

-3-BIT MSB THERMOMETER DAC 4- BIT BINARY DAC

OUTPUT

(A)

(B) CURRENT- SOURCE BASED

IOUT

IOUT

IOUT

IOUT

RESISTOR BASED

CONVERTERS DIGITAL-TO-ANALOG CONVERTER ARCHITECTURES

6.21

LSBs may use binary-weighted current sources. It is extremely important that such DACs have low distortion at high frequency, and there are several important issues to be considered in their design. Two examples of segmented current-output DAC structures are shown in Figure 6.21. Figure 6.21A shows a resistor-based approach for the 7-bit DAC where the 3 MSBs are fully decoded, and the 4 LSBs are derived from an R-2R network. Figure 6.21B shows a similar implementation using current sources. The current source implementation is by far the most popular for today's high-speed reconstruction DACs. It is also often desirable to utilize more than one fully decoded thermometer section to make up the total DAC. Figure 6.22 shows a 6-bit DAC constructed from two fully decoded 3-bit DACs. As previously discussed, these current switches must be driven simultaneously from parallel latches in order to minimize the output glitch.

Figure 6.22: 6-Bit Current-Output Segmented DAC Based on Two 3-Bit Thermometer DACs

The AD9775 14-bit, 160-MSPS (input)/400-MSPS (output) TxDAC™ uses three sections of segmentation as shown in Figure 6.23. Other members of the AD977x-family and the AD985x-family also use this same basic core. The first 5 bits (MSBs) are fully decoded and drive 31 equally weighted current switches, each supplying 512 LSBs of current. The next 4 bits are decoded into 15 lines which drive 15 current switches, each supplying 32 LSBs of current. The 5 LSBs are latched and drive a traditional binary-weighted DAC which supplies 1 LSB per output level. A total of 51 current switches and latches are required to implement this ultra low glitch architecture.

I I I I I I I I 8

-3-BIT MSB THERMOMETER DAC 3- BIT LSB THERMOMETER DAC

CURRENT OUTPUT

I 8

I 8

I 8

I 8

I 8

I 8

IOUT

IOUT

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