Scarica compendio istruzioni java e più Esercizi in PDF di Programmazione Java solo su Docsity!
Intel 80386 Instruction Subset Compendium
Corso di Reti Logiche e Calcolatori
Fabrizio Angiulli, Fabio Fassetti
1 DATA MOVEMENT INSTRUCTIONS
1.1 General-Purpose Data Movement Instructions
MOV { Move Data
Instruction Clocks Description MOV r/m8,r8 2/2 Move byte register to r/m byte MOV r/m16,r16 2/2 Move word register to r/m word MOV r/m32,r32 2/2 Move dword register to r/m dword MOV r8,r/m8 2/4 Move r/m byte to byte register MOV r16,r/m16 2/4 Move r/m word to word register MOV r32,r/m32 2/4 Move r/m dword to dword register MOV reg8,imm8 2 Move immediate byte to register MOV reg16,imm16 2 Move immediate word to register MOV reg32,imm32 2 Move immediate dword to register MOV r/m8,imm8 2/2 Move immediate byte to r/m byte MOV r/m16,imm16 2/2 Move immediate word to r/m word MOV r/m32,imm32 2/2 Move immediate dword to r/m dword
Flags Affected: None
XCHG { Exchange Register/Memory with Register
Instruction Clocks Description XCHG r/m8,r8 3 Exchange byte register with r/m byte XCHG r8,r/m8 3/5 Exchange byte register with r/m byte XCHG r/m16,r16 3 Exchange word register with r/m word XCHG r16,r/m16 3/5 Exchange word register with r/m word XCHG r/m32,r32 3 Exchange dword register with r/m dword XCHG r32,r/m32 3/5 Exchange dword register with r/m dword
Flags Affected: None
1.2 Stack Manipulation Instructions
PUSH { Push Operand onto the Stack
Instruction Clocks Description PUSH r/m16 2/5 Push r/m word onto the top of stack PUSH r/m32 2/5 Push r/m dword onto the top of stack PUSH imm16 2 Push immediate word onto the top of stack PUSH imm32 2 Push immediate dword onto the top of stack
Operation: PUSH decrements the stack pointer by 2 if the operand-size attribute of the instruction is 16 bits; otherwise, it decrements the stack pointer by 4. PUSH then places the operand on the new top of stack, which is pointed to by the stack pointer.
Flags Affected: None
POP { Pop a Word from the Stack
Instruction Clocks Description POP r/m16 4/5 Pop top of stack into r/m word POP r/m32 4/5 Pop top of stack into r/m dword
Operation: POP replaces the previous contents of the memory or the register with the word or the double word on the top of the 80386 stack, addressed by SS:SP (address-size attribute of 16 bits) or SS:ESP (addres-size attribute of 32 bits). The stack pointer SP is incremented by 2 for an operand-size of 16 bits or by 4 for an operand-size of 32 bits. It then points to the new top of stack.
Flags Affected: None
1.3 Type Conversion Instructions
MOVSX { Move with Sign-Extend
Instruction Clocks Description MOVSX r16,r/m8 3/6 Move byte to word with sign-extend MOVSX r32,r/m8 3/6 Move byte to dword, sign-extend MOVSX r32,r/m16 3/6 Move word to dword, sign-extend
Flags Affected: None
MOVZX { Move with Zero-Extend
Instruction Clocks Description MOVZX r16,r/m8 3/6 Move byte to word with zero-extend MOVZX r32,r/m8 3/6 Move byte to dword, zero-extend MOVZX r32,r/m16 3/6 Move word to dword, zero-extend
Flags Affected: None
2 BINARY ARITHMETIC INSTRUCTIONS
2.1 Addition and Subtraction Instructions
ADD { Add
Instruction Clocks Description ADD r/m8,imm8 2/7 Add immediate byte to r/m byte ADD r/m16,imm16 2/7 Add immediate word to r/m word ADD r/m32,imm32 2/7 Add immediate dword to r/m dword ADD r/m16,imm8 2/7 Add sign-extended immediate byte to r/m word ADD r/m32,imm8 2/7 Add sign-extended immediate byte to r/m dword ADD r/m8,r8 2/7 Add byte register to r/m byte ADD r/m16,r16 2/7 Add word register to r/m word ADD r/m32,r32 2/7 Add dword register to r/m dword ADD r8,r/m8 2/6 Add r/m byte to byte register ADD r16,r/m16 2/6 Add r/m word to word register ADD r32,r/m32 2/6 Add r/m dword to dword register
Flags Affected: OF, SF, ZF and CF.
DEC { Decrement by 1
Instruction Clocks Description DEC r/m8 2/6 Decrement r/m byte by 1 DEC r/m16 2/6 Decrement r/m word by 1 DEC r/m32 2/6 Decrement r/m dword by 1
Flags Affected: OF, SF, ZF.
2.2 Comparison and Sign Change Instruction
CMP { Compare Two Operands
Instruction Clocks Description CMP r/m8,imm8 2/5 Compare immediate byte to r/m byte CMP r/m16,imm16 2/5 Compare immediate word to r/m word CMP r/m32,imm32 2/5 Compare immediate dword to r/m dword CMP r/m16,imm8 2/5 Compare sign extended immediate byte to r/m word CMP r/m32,imm8 2/5 Compare sign extended immediate byte to r/m dword CMP r/m8,r8 2/5 Compare byte register to r/m byte CMP r/m16,r16 2/5 Compare word register to r/m word CMP r/m32,r32 2/5 Compare dword register to r/m dword CMP r8,r/m8 2/6 Compare r/m byte to byte register CMP r16,r/m16 2/6 Compare r/m word to word register CMP r32,r/m32 2/6 Compare r/m dword to dword register
Flags Affected: OF, SF, ZF and CF.
NEG { Two's Complement Negation
Instruction Clocks Description NEG r/m8 2/6 Two's complement negate r/m byte NEG r/m16 2/6 Two's complement negate r/m word NEG r/m32 2/6 Two's complement negate r/m dword
Flags Affected: CF is set to 1, unless the operand is zero, in which case CF is cleared to 0. OF, SF and ZF.
2.3 Multiplication Instructions
MUL { Unsigned Multiplication of AL or AX
Instruction Clocks Description MUL AL,r/m8 9-14/12-17 Unsigned multiply (AX AL * r/m byte) MUL AX,r/m16 9-22/12-25 Unsigned multiply (DX:AX AX * r/m word) MUL EAX,r/m32 9-38/12-41 Unsigned multiply (EDX:EAX EAX * r/m dword)
Flags Affected: CF and OF as follows
A byte operand is multiplied by AL; the result is left in AX. The carry and over ow ags are set to 0 if AH is 0; otherwise, they are set to 1.
A word operand is multiplied by AX; the result is left in DX:AX. DX contains the high-order 16 bits of the product. The carry and over ow ags are set to 0 if DX is 0; otherwise, they are set to 1.
A doubleword operand is multiplied by EAX and the result is left in EDX:EAX. EDX contains the high-order 32 bits of the product. The carry and over ow ags are set to 0 if EDX is 0; otherwise, they are set to 1.
SF and ZF are unde ned.
IMUL { Signed Multiply
Instruction Clocks Description IMUL r/m8 9-14/12-17 AX AL * r/m byte IMUL r/m16 9-22/12-25 DX:AX AX * r/m word IMUL r/m32 9-38/12-41 EDX:EAX EAX * r/m dword IMUL r16,r/m16 9-22/12-25 word register word register * r/m word IMUL r32,r/m32 9-38/12-41 dword register dword register * r/m dword IMUL r16,r/m16,imm8 9-14/12-17 word register r/m16 * sign-extended immediate byte IMUL r32,r/m32,imm8 9-14/12-17 dword register r/m32 * sign-extended immediate byte IMUL r16,imm8 9-14/12-17 word register word register * sign-extended immediate byte IMUL r32,imm8 9-14/12-17 dword register dword register * sign-extended immediate byte IMUL r16,r/m16,imm16 9-22/12-25 word register r/m16 * immediate word IMUL r32,r/m32,imm32 9-38/12-41 dword register r/m32 * immediate dword IMUL r16,imm16 9-22/12-25 word register r/m16 * immediate word IMUL r32,imm32 9-38/12-41 dword register r/m32 * immediate dword
Flags Affected: IMUL clears the over ow and carry ags under the following conditions:
Instruction Form Condition for Clearing CF and OF r/m8 AL = sign-extend of AL to 16 bits r/m16 AX = sign-extend of AX to 32 bits r/m32 EDX:EAX = sign-extend of EAX to 32 bits r16,r/m16 Result exactly ts within r r/32,r/m32 Result exactly ts within r r16,r/m16,imm16 Result exactly ts within r r32,r/m32,imm32 Result exactly ts within r
SF and ZF are unde ned.
2.4 Division Instructions
DIV { Unsigned Divide
Instruction Clocks Description DIV r/m8 14/17 Unsigned divide AX by r/m byte (AL=Quo, AH=Rem) DIV r/m16 22/25 Unsigned divide DX:AX by r/m word (AX=Quo, DX=Rem) DIV r/m32 38/41 Unsigned divide EDX:EAX by r/m dword (EAX=Quo, EDX=Rem)
Flags Affected: OF, SF, ZF and CF are unde ned.
IDIV { Signed Divide
Instruction Clocks Description IDIV r/m8 19 Signed divide AX by r/m byte (AL=Quo, AH=Rem) IDIV r/m16 27 Signed divide DX:AX by EA word (AX=Quo, DX=Rem) IDIV r/m32 43 Signed divide EDX:EAX by DWORD byte (EAX=Quo, EDX=Rem)
Flags Affected: OF, SF, ZF and CF are unde ned.
Flags Affected: None
3.2 Shift Instructions
SAL/SAR/SHL/SHR { Shift Instructions
Instruction Clocks Description SAL r/m8,1 3/7 Multiply r/m byte by 2, once SAL r/m8,CL 3/7 Multiply r/m byte by 2, CL times SAL r/m8,imm8 3/7 Multiply r/m byte by 2, imm8 times SAL r/m16,1 3/7 Multiply r/m word by 2, once SAL r/m16,CL 3/7 Multiply r/m word by 2, CL times SAL r/m16,imm8 3/7 Multiply r/m word by 2, imm8 times SAL r/m32,1 3/7 Multiply r/m dword by 2, once SAL r/m32,CL 3/7 Multiply r/m dword by 2, CL times SAL r/m32,imm8 3/7 Multiply r/m dword by 2, imm8 times SAR r/m8,1 3/7 Signed divide^(1) r/m byte by 2, once SAR r/m8,CL 3/7 Signed divide^(1) r/m byte by 2, CL times SAR r/m8,imm8 3/7 Signed divide^(1) r/m byte by 2, imm8 times SAR r/m16,1 3/7 Signed divide^(1) r/m word by 2, once SAR r/m16,CL 3/7 Signed divide^(1) r/m word by 2, CL times SAR r/m16,imm8 3/7 Signed divide^(1) r/m word by 2, imm8 times SAR r/m32,1 3/7 Signed divide^(1) r/m dword by 2, once SAR r/m32,CL 3/7 Signed divide^(1) r/m dword by 2, CL times SAR r/m32,imm8 3/7 Signed divide^(1) r/m dword by 2, imm8 times SHL r/m8,1 3/7 Multiply r/m byte by 2, once SHL r/m8,CL 3/7 Multiply r/m byte by 2, CL times SHL r/m8,imm8 3/7 Multiply r/m byte by 2, imm8 times SHL r/m16,1 3/7 Multiply r/m word by 2, once SHL r/m16,CL 3/7 Multiply r/m word by 2, CL times SHL r/m16,imm8 3/7 Multiply r/m word by 2, imm8 times SHL r/m32,1 3/7 Multiply r/m dword by 2, once SHL r/m32,CL 3/7 Multiply r/m dword by 2, CL times SHL r/m32,imm8 3/7 Multiply r/m dword by 2, imm8 times SHR r/m8,1 3/7 Unsigned divide r/m byte by 2, once SHR r/m8,CL 3/7 Unsigned divide r/m byte by 2, CL times SHR r/m8,imm8 3/7 Unsigned divide r/m byte by 2, imm8 times SHR r/m16,1 3/7 Unsigned divide r/m word by 2, once SHR r/m16,CL 3/7 Unsigned divide r/m word by 2, CL times SHR r/m16,imm8 3/7 Unsigned divide r/m word by 2, imm8 times SHR r/m32,1 3/7 Unsigned divide r/m dword by 2, once SHR r/m32,CL 3/7 Unsigned divide r/m dword by 2, CL times SHR r/m32,imm8 3/7 Unsigned divide r/m dword by 2, imm8 times
Flags Affected: OF is set only if the single-shift forms of the instructions are used. For left shifts, OF is set to 0 if the high bit of the answer is the same as the result of the carry ag (i.e., the top two bits of the original operand were the same); OF is set to 1 if they are different. For SAR, OF is set to 0 for all single shifts. For SHR, OF is set to the high-order bit of the original operand. OF is unde ned for multiple shifts. CF receives a copy of the bit that was shifted from one end to the other. ZF and SF
3.3 Double-Shift Instructions
SHRD { Double Precision Shift Right
Instruction Clocks Description SHRD r/m16,r16,imm8 3/7 r/m16 gets SHR of r/m16 concatenated with r SHRD r/m32,r32,imm8 3/7 r/m32 gets SHR of r/m32 with r SHRD r/m16,r16,CL 3/7 r/m16 gets SHR of r/m16 concatenated with r SHRD r/m32,r32,CL 3/7 r/m32 gets SHR of r/m32 concatenated with r
Operation:
SHRD shifts the rst operand provided by the r/m eld to the right as many bits as speci ed by the count operand. The second operand (r16 or r32) provides the bits to shift in from the left (starting with bit 31). The result is stored back into the r/m operand. The register remains unaltered. The count operand is provided by either an immediate byte or the contents of the CL register. These operands are taken MODULO 32 to provide a number between 0 and 31 by which to shift. Because the bits to shift are provided by the speci ed register, the operation is useful for multi-precision shifts (64 bits or more).
Flags Affected:
CF is set to the value of the last bit shifted out. OF is left unde ned. SF and ZF.
SHLD { Double Precision Shift Left
Instruction Clocks Description SHLD r/m16,r16,imm8 3/7 r/m16 gets SHL of r/m16 concatenated with r SHLD r/m32,r32,imm8 3/7 r/m32 gets SHL of r/m32 concatenated with r SHLD r/m16,r16,CL 3/7 r/m16 gets SHL of r/m16 concatenated with r SHLD r/m32,r32,CL 3/7 r/m32 gets SHL of r/m32 concatenated with r
Operation: SHLD shifts the rst operand provided by the r/m eld to the left as many bits as speci ed by the count operand. The second operand (r16 or r32) provides the bits to shift in from the right (starting with bit 0). The result is stored back into the r/m operand. The register remains unaltered. The count operand is provided by either an immediate byte or the contents of the CL register. These operands are taken MODULO 32 to provide a number between 0 and 31 by which to shift. Because the bits to shift are provided by the speci ed registers, the operation is useful for multiprecision shifts (64 bits or more).
Flags Affected:
CF is set to the value of the last bit shifted out. OF is left unde ned. SF and ZF.
3.4 Rotate Instructions
ROL/ROR { Rotate
Instruction Clocks Description ROL r/m8,1 3/7 Rotate 8 bits r/m byte left once ROL r/m8,CL 3/7 Rotate 8 bits r/m byte left CL times ROL r/m8,imm8 3/7 Rotate 8 bits r/m byte left imm8 times ROL r/m16,1 3/7 Rotate 16 bits r/m word left once ROL r/m16,CL 3/7 Rotate 16 bits r/m word left CL times ROL r/m16,imm8 3/7 Rotate 16 bits r/m word left imm8 times ROL r/m32,1 3/7 Rotate 32 bits r/m dword left once ROL r/m32,CL 3/7 Rotate 32 bits r/m dword left CL times ROL r/m32,imm8 3/7 Rotate 32 bits r/m dword left imm8 times ROR r/m8,1 3/7 Rotate 8 bits r/m byte right once ROR r/m8,CL 3/7 Rotate 8 bits r/m byte right CL times ROR r/m8,imm8 3/7 Rotate 8 bits r/m word right imm8 times ROR r/m16,1 3/7 Rotate 16 bits r/m word right once ROR r/m16,CL 3/7 Rotate 16 bits r/m word right CL times ROR r/m16,imm8 3/7 Rotate 16 bits r/m word right imm8 times ROR r/m32,1 3/7 Rotate 32 bits r/m dword right once ROR r/m32,CL 3/7 Rotate 32 bits r/m dword right CL times ROR r/m32,imm8 3/7 Rotate 32 bits r/m dword right imm8 times
Operation: The rotate is repeated the number of times indicated by the second operand, which is either an immediate number or the contents of the CL register. To reduce the maximum instruction execution time, the 80386 does not allow rotation counts greater than 31. If a rotation count greater than 31 is attempted, only the bottom ve bits of the rotation are used.
Flags Affected:
OF only for single rotates; OF is unde ned for multi-bit rotates; for left shifts/rotates, the CF bit after the shift is XORed with the high-order result bit. For right shifts/rotates, the high-order two bits of the result are XORed to get OF. CF receives a copy of the bit that was shifted from one end to the other.
RET { Return from Procedure
Instruction Clocks Description RET 10 Return (near) to caller RET imm16 10 Return (near), pop imm16 bytes of parameters
Flags Affected: None
5 MISCELLANEOUS INSTRUCTIONS
5.1 Address Calculation Instructions
LEA { Load Effective Address
Instruction Clocks Description LEA r16, m 2 Store effective address for m in register r LEA r32, m 2 Store effective address for m in register r
Flags Affected: None
