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Synchronous LOGIC^ Design^2
output cannot^ be^ determined
FIRST :^ PROBLEMATIC CIRCUITS^ simply by
looking
at inputs
* Y Z
s (^) output of third inverter
is fed back to first inverter
< propogation (^) delay of^ Ins
so,^ what^ does^ it do^?
O (^) Suppose Node^ X^ is^ initially 0.^ Then^ Y^ =^1 , z^ =^0 & Hence X^ =^1 ,^ which^ is inconsistent with^ our^ original Assumption
& no stable states - >^ called :a stable/unstable
③ Actual^ behaviour^ of^ circuit
·
if X^ rises at time^ O^ , Y will fall at
Ins ↓ = (^) -
Z will rise at 2ns , X will fall again
at (^) 5 ns
· i^ I'sk's'78^ Timecas In^ turn^ ,Y will^ rise^ at^ 44s^ , z will (^) fall at 3 ng
This is^ a^ RING^ OSCILLATOR:^
S X (^) rises (^) again at^ 6ns &^ repeat
- Each node (^) oscillates betweenOf 1 with a^ period (repetition time)^ of Gns summary :
period depends^ on^ propogation
e Ring Oscillator is^ a (^) sequential delay
(which depends on^ inverter^ circuit^ with^ ZERO^ inputs^
& ONE
manufacture - power/voltage/temp) output^ that^ changes periodically
PROBLEMATIC CIRCUIT O (^) ↓
Random
person claims their D^ latch is^ better^ than (^) , bes^ it^ uses lesser^ gates Y ↓ in=>
NI =^ CK^ - D CLK D ①prev Q
O 00 O Q (^) O O I I K 3 O I^ O^ O
N2 : CLK · Oprev O^ I^ I
I 00!
①prev
10 I^ O
11 I I^ i^ i Investigation : does (^) it work?
- let's (^) first see how it works this is^ called^ a^ race condition
circuit fails as certain (^) gates are slower than others Dissecting failure : Suppose D^ = (^) CLk =^1. Latch is (^) transparent and^ passes D through to^ make^ =1. (^). Now (^) , CLK^ falls (^). latch should remember it's old value^ , keeping Q^ :^ / 3 However^ , (^) suppose the^ delay through inverterclk^ to^ EK is (^) rather long compared^ to^ the^ delays^ of^
the AND O OR
gates
4 Then (^) , nodes^ N1 and^ Q^ may both^ fall^ beforeEk^ rises (^4) In such a case (^) , N2 (^) will never rise and Q^ is stuck at^0 This is (^) an (^) example of asychronous circuit design
S
E
behaviour of circuits
2
depends on^ which^ of^ two
outputs are^ fed^ back^ ~ paths through logic gates is into (^) inputs infamous for^ fastest^ I
- one circuit (^) may work while a having
race conditions^
seemingly similar^ one^ w^ diff
zu
- the circuit (^) may work (^) only at logic gates (diff^ delays) may not certain temperatures/voltages
where delays are just right
- (^) xtremely difficult to^ track
Rules (^) of synchronous sequential^
circuit :
~ A^ circuit is^ a^ sychronous sequential circuit^ if^ it^ consists^ of^ interconn^ - ected circuit elements such^ that storage elements^ to^ hold^ binary^ data (^) (composed of
- collection^ of^ Flip-flops^ ,^ latches^ ,^ inverters^ ,^ bistables)
Every circuit^ element^ is^ either^ a^ register or^ a^ combinational^ circuit
At least one circuit element is a
register (^) common (^) sequential circuit All (^) registers receive the (^) same clock (^) signal
- finite state machines CFSM)
- pipelines Every cyclic path contains^ one^ register CLI Simplest (^) synchronous sequential circuit^ it^ has^ one s (^) D (^) Q S input(D),^ one^
clock (CLk) , one output(Q) & 2 states^ no, 13
Next state (^) current state
current state is called s , next state is called IS']
Flip-Flup
which (^) of these^ are (^) synchronous sequential circuits^?
CL17 K
a)
q b)^ [
! Ans :^ combi^ , no^ registers
Ans: simple sequential circuit^ w/o^ Ans^ :^ neither^ combinor^ sequential ,^ latch^ is
feedback neither^ register^ nor^ combi^ circuit d) (^) , G " CLK ↓ a & CLK G f) (^) E
Ans : synchronous sequential Anc : synchronous sequential Ans^
: neither sequential nor combi , cyclic
(FSM) (^) CFSM) path^ from^ output^ of^ combilogic
back to input of the same logic
but no register
CH) CLK CLK CLK^ -^2 inverters^ delay^ CLK signal received^ by
- h)^ and^ register
Q Q [
Ans : synchronous sequential (^) (pipeline) Ans :^ not (^) synchronous sequential , (^) although same^ (LK, there are 2 inverters^ thus^ delaying CLI
Synchronous vs^ Asynchronous Circuits
Asynchronous in^ theory is
7 more^ general^ than can (^) use (^) any kind S S 3 22 synchronous why^
of feedback (just
like (^) how not^ limited^ by^ clocked analog circuits registers
can use any ocassionally^ necessary
voltage as^ opposed to^ Synchronous circuits when^ communicating
digital (^ are^ easier^ to^ design^ & use (^) between systems with than (^) asychronous circuits different clocks^ or receiving in puts at arbitrary times
