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8310f
Typical applicaTion
FeaTures DescripTion
100VIN Forward Converter
Controller
The LT®8310 is a simple-to-use resonant reset forward converter controller that drives the gate of a low side N-channel MOSFET from an internally regulated 10V sup- ply. The LT8310 features duty mode control that generates a stable, regulated, isolated output using a single power transformer. With the addition of output voltage feedback, via opto-coupler (isolated) or directly wired (nonisolated), current mode regulation is activated, improving output accuracy and load response. The flexibility to choose transformer turns ratio makes high step-down or step-up ratios possible without operating at duty cycle extremes. The user can program the switching frequency from 100kHz to 500kHz to optimize efficiency, performance or external component size. A synchronous output is available for controlling secondary side synchronous rectification to improve efficiency. User programmable protection features include monitors on input voltage (UVLO and OVLO) and switch current (overcurrent limit). The LT8310 soft-start feature helps protect the transformer from flux saturation.
78 Watt Isolated Forward Converter, ±8% VOUT
Output Voltage Load Regulation
applicaTions
n (^) Input Voltage Range: 6V to 100V n (^) Duty Mode Control Regulates an Isolated Output without an Opto n (^) High Efficiency Synchronous Control n (^) Short-Circuit (Hiccup Mode) Overcurrent Protection n (^) Programmable OVLO and UVLO with Hysteresis n (^) Programmable Frequency (100kHz to 500kHz) n (^) Synchronizable to an External Clock n (^) Positive or Negative Polarity Output Voltage Feedback with a Single FBX Pin n (^) Programmable Soft-Start n (^) Low Shutdown Current < 1μA n (^) Available in FE20 TSSOP with HV Pin Spacing
n (^) Industrial, Automotive and Military Systems n (^) 48V Telecommunication Isolated Power Supplies n (^) Isolated and Nonisolated DC/DC Converters L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
LT
UVLO
OVLO
DFILT RT SS
SYNC
INTVCC RDVIN
GATE SENSE GND
V (^) C
NC NC FBX
SOUT
4.7μF
VIN 36V TO 72V
V (^) OUT 12V 0.6A TO 6.5A
–VOUT
–V (^) IN
V (^) IN
86.6k
1.74k
1.43k
0.025Ω 102k 1%
49.9k 200kHz
2.2μF 100V × 4
47μH 2:
150pF NPO
10nF^ 8310 TA01a
1μF 100V
0.47μF (^) NC
22μF × 8 100μF
IOUT (A)
0
V^ OUT
(V)
3 8310 TA01b
1 2 4
5 6 7
VIN = 72V V (^) IN = 48V V (^) IN = 36V
8310f
absoluTe MaxiMuM raTings pin conFiguraTion
V IN , UVLO ...............................................................100V
INTVCC, RDVIN, SYNC ..............................................20V
DFILT...........................................................................8V
VC, OVLO, SS, RT ........................................................3V
FBX ................................................................. –3V to 3V SENSE ....................................................... –0.3V to 0.3V GATE, SOUT ..........................................................Note 3 Operating Junction Temperature Range (Notes 4, 5) LT8310E ............................................. –40°C to 125°C LT8310I.............................................. –40°C to 125°C LT8310H ............................................ –40°C to 150°C LT8310MP ......................................... –55°C to 150°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature Range (Soldering, 10 sec)........ 300°C
(Notes 1, 2)
FE PACKAGE 20-LEAD PLASTIC TSSOP
1 3 5 6 7 8 9
10
TOP VIEW 20
18
16 15 14 13 12 11
UVLO
OVLO
DFILT RT SYNC SS V (^) C FBX
NC
VIN
RDVIN INTVCC GATE SENSE NC SOUT
21 GND
TJMAX = 125°C (E-, I-GRADES), TJMAX = 150°C (H-GRADE), θJC = 10°C/W, θJA = 38°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO THE GROUND PLANE
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE* LT8310EFE#PBF LT8310EFE#TRPBF LT8310FE 20-Lead Plastic TSSOP –40°C to 125°C LT8310IFE#PBF LT8310IFE#TRPBF LT8310FE 20-Lead Plastic TSSOP –40°C to 125°C LT8310HFE#PBF LT8310HFE#TRPBF LT8310FE 20-Lead Plastic TSSOP –40°C to 150°C
LT8310MPFE#PBF LT8310MPFE#TRPBF LT8310FE 20-Lead Plastic TSSOP –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
8310f
PARAMETER CONDITIONS MIN TYP MAX UNITS Feedback Mode Threshold Voltage (Below = Duty Mode/Above = Current Mode)
FBX > 0V FBX < 0V
–0.
–0.
–0.
V V Feedback Mode Threshold Hysteresis FBX > 0V FBX < 0V
20 20
mV mV FBX Pin Input Current FBX = 1.6V FBX = –0.8V –
70 0
100 100
nA nA Transconductance (ΔIVC /ΔVFBX) 250 μA/V VC Source Current V (^) FBX = 0V, V (^) VC = 1.3V –14 μA V (^) C Sink Current V (^) FBX = 1.7V, V (^) VC = 1.3V VFBX = –0.85V, VVC = 1.3V
13 11
μA μA V (^) C Pin Output Impedance 3.3 MΩ V (^) C Pin Current Mode Gain 5 V/V Gate Driver GATE Rise Time C (^) GATE = 3.3nF 30 ns GATE Fall Time C (^) GATE = 3.3nF 27 ns GATE Low Voltage 0.05 V GATE High Voltage INTV (^) CC
V
Current Sense SENSE Pin Maximum Current Threshold l^115 125 135 mV SENSE Pin Input Current –200 μA Oscillator Switching Frequency RT = 100k to GND, VSS ≥ 2.9V R (^) T = 33.2k to GND, VSS ≥ 2.9V R (^) T = 20k to GND, VSS ≥ 2.9V
l l l
95 285 475
100 300 500
105 315 525
kHz kHz kHz Switching Frequency Line Regulation VIN = 6V to 100V 0.01 % RT Pin Voltage VSS = 3V 0.8 1.0 1.3 V Frequency Foldback Foldback = (f (^) OSC at VSS = 1.15V)/fOSC(NOM)
VSS = 1.15V 0.15 0.20 0.25 Hz/Hz
SYNC Pin Input High Threshold Voltage l 2.00 V SYNC Pin Input Low Threshold Voltage l^ 1.00 V SYNC Pin Input Resistance SYNC = 2V 200 kΩ SYNC Frequency Operating Range RT = 33.2k l 260 400 kHz Minimum SYNC High Setup Time fSW = 400kHz l^250 ns Minimum SYNC Low Hold Time fSW = 400kHz l 250 ns SOUT Driver SOUT Rise Time CSOUT = 1nF 20 ns SOUT Fall Time C (^) SOUT = 1nF 25 ns SOUT Low Voltage 0.05 V SOUT High Voltage INTV (^) CC
V
elecTrical characTerisTics The^ l^ denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T (^) A = 25°C, VIN = 24V, UVLO = 24V, OVLO = 0V, SYNC = 0V, SENSE = 0V, unless otherwise noted.
8310f
elecTrical characTerisTics The^ l^ denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T (^) A = 25°C, VIN = 24V, UVLO = 24V, OVLO = 0V, SYNC = 0V, SENSE = 0V, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are relative to GND unless otherwise noted. All pin currents are defined positive into the pin unless otherwise noted. Note 3: Do not apply a positive or negative voltage or current source to the GATE or SOUT pins, otherwise permanent damage may occur. Note 4: The LT8310E is guaranteed to meet performance specifications from the 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8310I is guaranteed over the full −40°C to 125°C operating junction temperature range. The LT8310H is guaranteed over the full –40°C to 150°C operating junction temperature range. The LT8310MP is guaranteed over the full –55°C to 150°C operating junction temperature range. Operating lifetime is derated at junction temperatures greater than 125°C.
Note 5: The LT8310 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum junction temperature may impair device reliability. Note 6: VSET = V (^) INTVCC – V (^) RDVIN. Note 7: Line regulation in duty mode control applications is constrained by the accuracy of the RDVIN pin input current, the duty mode control gain, and the external set resistor, RSET. RSET should be specifiied to 1% or better. Note 8: See the Timing Diagrams section.
PARAMETER CONDITIONS MIN TYP MAX UNITS SOUT-to-GATE Delay (tPRE) SOUT Falling to GATE Rising (Note 8) l 190 240 300 ns GATE-to-SOUT Delay (tPOST) GATE Falling to SOUT Rising (Note 8) l^0 12 25 ns Soft-Start SS Active Switching Level (GATE Switches) 0.95 1.00 1.05 V SS Frequency Foldback Complete fOSC within Specified Limits l 2.5 V SS Pin Current (Note 8) Soft-Up Slow Wake Hard-Down, VSS = 0.4V
l l
μA μA mA SS Reset Threshold Voltage 0.27 V
8310f
SENSE Overcurrent Threshold Voltage vs Temperature
INTV (^) CC Current Limit vs Input Voltage
Typical perForMance characTerisTics
VIN Quiescent Current vs Temperature
GATE Driver Transition Time vs Capacitance
SOUT Driver Transition Time vs Capacitance
FBX Regulation Voltage vs Temperature
INTV (^) CC Voltage vs Temperature and Load Current
INTV (^) CC Dropout Voltage vs Load Current, Temperature
INTVCC Current Limit vs Temperature
T (^) A = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–75 –50 –25 0 25 50 75 100 125 150
VSENSE
(V)
8310 G
175
0
2
4
ERROR (%)
TA, AMBIENT TEMPERATURE (°C)
VINTVCC
(V) 10.
125 8310 G
–50 –25 0 25 50 75 100 150 175
SHUTDOWN AT TJ ≈ 165°C
LOAD = 1mA LOAD = 10mA LOAD = 20mA
INTVCC LOAD (mA)
0 0
DROPOUT VOLTAGE (V)
4 8 12 16 8310 G
20 24
TA = 125°C
TA = –65°C
TA = 25°C
TA, AMBIENT TEMPERATURE (°C)
–I^ INTVCC
(mA) 32
34
36
125 8310 G
30
28
26 –50 –25 0 25 50 75 100 150 175
VIN = 12V T (^) J ≈ T (^) A + 15°C
TEMPERATURE (°C)
–75 –50 –25 0 25 50 75 100 125 150
POSITIVE V
FBX
(V)
8310 G
1.568 (^175)
POSITIVE NEGATIVE
–0.
–0.
–0.
–0.
–0.
NEGATIVE V
FBX (^) (V)
TEMPERATURE (°C)
IVIN
(mA) (^) 4.
125150 8310 G
–50 –25 0 25 50 75100 175
GATE, SOUT PINS NOT SWITCHING
VIN (V)
0 20
–IINTVCC
(mA)
25
30
35
40
45
50
20 40 60 80 8310 G
100
INSTANTANEOUS FROM OFF, TA = TC = 25°C
THERMALLY SETTLED, T (^) A = 25°C
C (^) GATE (nF)
0
TIME (ns)
(^60)
80
100
20 8310 G
40
20
50
70
90
30
10 0 5 10 15 25
tRISE
VIN = 48V fSW = 100kHz
t (^) FALL
CSOUT (nF)
0
TIME (ns)
(^60)
80
100
8310 G
40
20
50
70
90
30
10 0 1.5 3.0 4.5 7.
tFALL
VIN = 48V fSW = 100kHz
tRISE
8310f
Typical perForMance characTerisTics^ TA = 25°C, unless otherwise noted.
Driver Nonoverlap Delays vs Temperature Set Current vs Soft-Start Voltage
Switching Frequency (Normalized) vs Soft-Start Voltage
GATE Duty Cycle (Normalized) vs Soft-Start Voltage
Output Voltage Transient Response (Typical Applications, Pages 1 and 31)
TEMPERATURE (°C)
tDLY
(ns) (^150)
200
250
300
125 8310 G
100
50
125
175
225
275
75
25 0 –50 –25 0 25 50 75100 150175
SOUT FALL TO GATE RISE
GATE FALL TO SOUT RISE
VSS (V)
0 0
IRDVIN
(μA)
5
10
15
20
25
0.5 1.0 1.5 2. 8310 G
2.5 3. VSS (V)
0
0 –0. 1.5 2. 8310 G
0.5 1.0 2.0 3.
fSW
/fSW(NOM)
(kHz/kHz)
V (^) SS (V)
0
0 –0. 1.5 2. 8310 G
0.5 1.0 2.0 3.
DUTY/DUTY (NORM) (%/%)
100kHz 300kHz 500kHz
VIN = 48V 1ms/DIV 8310 G I (^) OUT = 4.5A TO 6.5A TO 4.5A
V (^) OUT 1V/DIV
8310f
pin FuncTions
SENSE (Pin 13): Switch Current Sense Input. Positive input of the low side current sense to the control loops and the overcurrent comparator. Kelvin-connect this pin to the sense resistor at the source of the N-channel MOSFET switch. Exceeding 125mV at this pin triggers an overcur- rent fault, and sends the system into fast shutdown, slow wake-up, and soft-start. GATE (Pin 14): Switch Control Output. Low side switch drive (GND to INTVCC) for external N-channel MOSFET. The maximum duty cycle is limited to 78% (typ) because reso- nant reset forward converters require time for transformer flux to reset. Actively pulled to GND during shutdown. INTVCC (Pin 15): Regulated Supply Output. A 10V LDO supply generated from V (^) IN and capable of supplying the GATE pin. Must be bypassed with a 4.7μF capacitor or higher. The regulator voltage can be externally driven up to 17V, as long as VIN ≥ V (^) INTVCC, to reduce internal power dissipation from V (^) IN or to accommodate more than 10V gate drive for high voltage N-channel MOSFETs. RDVIN (Pin 16): Duty Cycle Control Input. This pin sinks a precise 20μA in normal operation, but less during soft- start, when the duty cycle is folded back. Connect a resistor RSET between the INTV (^) CC and RDVIN pins to program the desired (no opto) application output voltage:
RSET =
NP
NS
VOUT
20μA
Resistor value accuracy contributes directly to the output voltage accuracy, choose appropriate tolerance. In current mode applications, feedback sets VOUT, therefore program RSET to set a maximum duty cycle guardrail that constrains the volt-seconds of flux in the transformer during transients. This pin must be connected to INTVCC by a resistor. VIN (Pin 18): Supply Input and System Input Voltage Sense. Input supply for the part; operational from 6V to 100V. Accurate duty cycle requires accurate sensing of the VIN voltage, so keep the connection to the transformer primary short to minimize resistive voltage drops. Bypass to GND with 1μF. NC (Pin 20): No Internal Connection. Connect to VIN. GND (Exposed Pad Pin 21): Ground. This pin also senses the negative terminal of the current sense resistor. Solder the exposed pad directly to the ground plane.
8310f
block DiagraM
CIN
CDFILT RT
UVLO
V^ IN
IREF
1.22V
V^ OUT
R3 R2 R
L
T1N :NP S
D
D
8310 F
CL
1
OVLO DFILT RT
C2 CREG M
Q R S
Q S R
RST DUTY RST PCM
SS DUTY CYCLEFOLDBACK20μA NOM.
0μATO 20μA
SS FREQUENCYFOLDBACK
DUTY RAMP CLOCK PULSESLOPECOMP
0.25V TO 1V +– 5.7μA
SYS UV
50μA
1.6V
NC
–0.2V
g^ m
= 250μA/V
FBX –0.8V 3V
HICCUP
FBX
CLK
HICCUPLOGIC
5μA
3V
1
1.25V
SYS OV
1
REG UV
gm^
= 25μA/V
4.75V
INTV
CC
+^
10V INTV
CC
V^ IN
RDVIN
17.4V
RISING HYST
0.45V FALLING HYST
–0.65V
REG OV
TIM165°C
DUTY LOOP RAMP GENERATOR
1V NOM.
DUTY LATCH
DUTY
PCM LATCH
PCM
GATE DRIVER
SYS OT
IREF
+^
+^
125mV
ISW MAX
FB MODESS LOW
I^ SUP
gm^
= 25μA/V
FB MODESS LOW
16 GATE
NC 15 V^ IN
18
÷ 12
V^ IN
RSET
V SET
RSENSE
SNS
SYS UVSYS OVSYS OTREG UVREG OVISW MAX
0
1
FBX OV
5 CSS
SS 8
V^ C FBX
FB MODE
(^610)
SYNC 7
100kHz TO 500kHzOSCILLATOR SLOPE COMPRAMP GENERATOR
PWMCONTROLLOGIC
200k
SS LOW
0.3V
0.27V 1V
SS CLAMPS V^ C 15μA
FAULT
INTV
CC^
–0.86V
FBX OV
1.72V
14
SOUT DRIVER
SOUT
11 SENSE
13 GND EXPOSED
PAD
21
3 9
A = 5
CRST
Figure 1. LT8310 Block Diagram Configured as a Nonsynchronous Duty Mode Converter
8310f
operaTion
INTRODUCTION
The LT8310 is a constant-frequency forward converter controller with a low side N-channel MOSFET gate driver and low side switch current sensing that offers two oper- ating modes: duty mode control and peak current mode control. Duty mode control that requires no output voltage feedback is targeted for (but not limited to) isolated duty mode control applications, to which it brings a simple schematic, low parts count, and only one isolation element, a transformer. In current mode control applications, feed- back determines the output voltage, but the duty control loop enforces a programmable relative maximum duty cycle that clamps the volt-seconds of core flux to avoid transformer saturation during transients. At all times the LT8310 also enforces an absolute maximum duty cycle that provides time to reset the core each switching period. With a patent pending architecture, the LT8310’s duty control loop imposes volt-second accuracy over the span of input voltage that translates into both accurate output voltage without feedback and protection from transformer saturation.
Duty Mode Control
The duty mode control loop compels a PWM duty cycle that is inversely proportional to the system input voltage, D(VIN) ∝ 1/V (^) IN, which is the correct function for a buck (or buck derived) converter to generate a constant output regardless of the line input. For a given scaling constant KD,
D(VIN ) =
KD [ V]
VIN
[1]
In a forward converter with transformer turns ration NP/NS,
VOUT =
D(VIN ) • VIN
NP / NS
KD
NP / NS
[2]
In the discussion that follows it will be helpful to refer to the Block Diagram in Figure 1. Duty mode control governs operation when the feedback pin (FBX) is tied to GND. It serves as an accurate volt-second clamp when current mode control governs operation because feedback is present. The system clock starts the PWM duty cycle by driving the GATE pin high to close the external MOSFET switch and initiating a timing ramp in the duty loop ramp generator. While GATE is high, current proportional to VIN discharges a capacitor (CDFILT) between the DFILT pin and GND; when GATE is pulled low, a fixed current charges it. The duty cycle ends when the ramp voltage plus some switch current feedback exceeds the DFILT voltage, at which point GATE falls and shuts off the primary-side switch until the start of the next period. The condition of the main switch (on or off, as indicated by GATE pin voltage) controls the sourcing and sinking of current at the DFILT pin. The voltage imposed between the INTV (^) CC and RDVIN pins, V (^) SET, establishes an inter- nal reference current (I (^) REF). During the switch on-time, D • tSW, a current proportional to the system input voltage VIN (which is sensed at the V (^) IN supply pin) is subtracted from the reference current and driven at DFILT. During the switch off-time, (1-D) • tSW, only the reference current is driven. The external capacitor to GND at DFILT (CDFILT) integrates the current. In steady-state operation with suf- ficient load, the feedback loop forces the net cycle current to zero, which produces a duty cycle inversely proportional to VIN (Equation 3), and ultimately a constant output voltage (Equation 4). An external resistor (RSET) between INTV (^) CC and RDVIN and a precise 20μA sink at RDVIN program VSET and thus, VOUT.
D =
12 • VSET
VIN
[3]
VOUT =
12 • VSET
NP / NS
[4]
8310f
operaTion
Several system operation and protection features are exclu- sive to current mode control. When the load is light, auto- matic pulse skipping allows the effective switching period to extend, which lowers the duty cycle without necessitating impractically narrow GATE pulses. If FBX pin overvoltage is detected during a cycle, the duty cycle ends, GATE falls, and the switch turns off, which allows the output voltage to coast down. When current mode control governs opera- tion, the duty loop circuitry acts as a relative maximum duty cycle clamp that protects the transformer from developing excessive volt-seconds of flux during transients and it limits the output voltage. This feature also allows the system to revert to duty mode control if FBX is grounded. The duty cycle clamp margin is user-programmable.
Common Operation and Protection Features A programmable soft-start pin (SS) controls the power-up time and folds back the switching frequency and the duty cycle during start-up to protect the transformer and to limit inrush current. A minimum on-time of 190ns (typ) ensures that the MOSFET switch has enough time to turn on reliably, and a maximum duty cycle of 78% guarantees time for core reset each cycle. The SYNC pin allows an external pulse signal to override the LT8310’s oscillator and set the switching period. The SOUT pin supplies a non-overlapping signal complementary to the GATE that may be used for synchronous converter applications. The SOUT pin driver has about 40% of the GATE pin’s drive strength, and may be used to drive a pulse transformer (isolated) for forced continuous mode (FCM) operation. Other protection mechanisms end the normal switching cycle or force system shutdown to protect the applica- tion circuit. The minimum and maximum V (^) IN operating thresholds are programmed at the UVLO and OVLO pins, respectively. Input voltages outside of the set limits shut down the system. Shutdown also occurs when the INTVCC regulator voltage goes above or below its operating range, and when the die temperature exceeds 165°C. The switch
With no output voltage feedback, the secondary-side LC filter might freely ring (depending on load resistance and parasitics) in response to load current steps; the primary- side switch current that feeds into the duty mode control loop limits the ringing. During the switch on-time, induc- tor current translates to switch current that is scaled and added to the timing ramp. Constant current is absorbed into the DC level of the DFILT voltage, which does not af- fect duty cycle, but changing current dynamically adjusts the duty cycle to dampen the ringing. The DFILT capacitor is chosen with respect to the output LC time constant (√L1•C (^) L) to track out the oscillation. The selection of this capacitor is discussed in the section, Compensating the Duty Mode Control Loop.
Duty mode control operation requires a minimum load in steady-state to balance the sum of the transformer mag- netization current and output inductor ripple current, see the section, Minimum Load Requirements.
Current Mode Control
To serve applications that require tighter output voltage regulation and faster load response, the LT8310 offers standard constant-frequency peak current mode control when output voltage feedback (opto-isolated or noniso- lated) is connected. The system clock starts the PWM duty cycle by driving the GATE pin high to close the external MOSFET switch. The switch current flows through the external current sensing resistor R (^) SENSE and generates a voltage proportional to the switch current. The current sense voltage is amplified and added to a stabilizing slope compensation ramp. When the resulting sum exceeds the control pin (V (^) C) voltage, the duty cycle ends, and the main switch is opened. The VC pin level is set by the error ampli- fier, which amplifies the difference between the reference voltage (1.6V or –0.8V, depending on the configuration) and the feedback pin (FBX) voltage. In this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation.
8310f
operaTion
D1 conducts, which imposes V (^) IN /(NP/NS) – V (^) OUT across inductor L1 (ignoring voltage drop across the diode), for the switch on-time, D • tSW. When the GATE signal goes low, the switch turns off, and the primary winding volt- age collapses as the primary current charges the reset resistor CRST. The switch node voltage (VSW) resonates past VIN, which takes the primary winding voltage nega- tive. The secondary winding voltage also goes negative, forward diode D1 turns off, and the inductor current flows through the catch diode, D2, which imposes –V (^) OUT (again ignoring diode drop) across inductor L1 for the switch off-time, (1 – D) • t (^) SW. The output voltage may be calculated by considering the volt-second balance in the inductor under steady-state conditions (Equation 5), and then solving for V (^) OUT. Equation 6 makes it clear that forcing the duty cycle to be inversely proportional to the input voltage would create a constant output voltage as desired.
VIN NP / NS
− VOUT
⎛ ⎝
⎜
⎞ ⎠
⎟ • D • TSW +(−VOUT ) • (1−D) • TSW = 0 [5]
VOUT = D • VIN NP / NS^ [6]
To keep the transformer from saturating, its core flux must be reset periodically. The LT8310 relies on resonant reset each cycle uses a capacitor between the switch node, SW, and ground (see Figure 2). When the main switch turns off at the end of the duty cycle, VSW ramps up to and beyond VIN, which cuts off secondary-side current and forces primary-side current to charge the switching node. Node SW resonates for half a sine wave until the transformer voltage and current are both zero, which leaves V (^) SW = V (^) IN until the next switch activation. Note that (1) the maximum voltage on the primary switch exceeds the input voltage, and may be well above it, and (2) ideally, the flux reset completes within the switch off-time before the next cycle begins. The LT8310 controller imposes an absolute maximum duty cycle that provides a predictable minimum off-time (at a given switching frequency) in which to reset the core.
8310f
INTVCC Regulator Bypassing and Operation
The GATE and SOUT pin drivers and other chip loads are powered from the INTVCC pin, which is an internally regulated supply. The internal low dropout regulator re- quires a capacitor from the INTVCC pin to GND for stable operation and to store the charge for the large GATE and SOUT switching currents; a 4.7μF capacitor is adequate for most applications. Choose a 16V rated low ESR, X7R ceramic capacitor for best performance. Place the capaci- tor close to the LT8310 to minimize the trace length both to the INTVCC pin and to the chip ground. In shutdown, the INTVCC pin sinks 125μA (typical) until the pin voltage falls below 4.75V.
An internal current limit on the INTVCC output protects the LT8310 from excessive on-chip power dissipation. The minimum specified current limit should be consid- ered when choosing the switching N-channel MOSFET and the operating frequency. Careful selection of a lower QG MOSFET allows higher GATE switching frequencies, which leads to smaller magnetics. SOUT switching current must be accounted for when that pin drives a MOSFET gate, but in typical applications where SOUT is unused or drives an AC-coupled pulse transformer, GATE switching dominates the steady-state regulator load and the SOUT current may be ignored. The MOSFET gate drive switching current required may be calculated using Equation 7, see the Thermal Considerations section for further information.
I (^) DRIVE = QG • fSW [7]
The INTVCC voltage tracks a few hundred millivolts below the supply voltage until the regulation loop closes when VIN exceeds about 10.5V. The INTVCC pin has its own undervoltage disable set to 4.75V (typical) that protects the external MOSFET from excessive power dissipation caused by not being fully enhanced. If the INTVCC pin drops below its undervoltage threshold, the GATE pin will be forced to GND, the SOUT pin will follow the INTVCC voltage, and the soft-start pin will be reset.
The regulator may be overdriven from external circuitry to reduce switching power dissipation in the LT8310 package, or to drive a MOSFET switch with a high threshold. The overdriven INTVCC pin voltage must be less than the IC supply to avoid back-driving the V (^) IN pin. The INTVCC pin
applicaTions inForMaTion
has its own overvoltage threshold set to 17.4V (typical) that disables the system to protect MOSFETs rated for VGS(MAX) = 20V, a common specification. As with undervoltage shutdown, the GATE pin will be forced to GND, the SOUT pin will follow the INTVCC voltage, and the soft-start pin will be reset. A 4.7μF 25V rated low ESR, X7R capacitor is recommended when INTVCC is overdriven.
Programming the System Turn-On and Turn-Off Thresholds The system undervoltage and overvoltage thresholds are programmed by a resistive voltage divider from VIN to UVLO and OVLO, respectively (Figure 4). The falling UVLO threshold,1.22V (nom), accurately sets the minimum op- erating VIN (Equation 8), below which the system goes into low power mode. A 5.7μA (typical) pull-down current that is active when the UVLO pin is below its falling threshold provides rising hysteresis that sets the minimum start- up VIN (Equation 9). The built-in comparator hysteresis contributes a small amount to the rising threshold as well.
VIN(UVLO FALLING) = 1.22V •
R3+R2+R
R2+R
⎟ [8]
VIN(UVLO RISING) = VIN(UVLO FALLING) + 5.7μA • R
R3 + R2 + R
R2 + R
⎝⎜^
⎠⎟^
[9]
The rising OVLO threshold, 1.25V (nom), accurately sets the maximum operating V (^) IN (Equation 10), above which the system stops switching and awaits soft-start. The built-in comparator hysteresis provides falling hysteresis that sets the maximum restart VIN (Equation 11).
Figure 4. Resistor Connections for System UVLO and OVLO Threshold Programming
GND
LT UVLO
OVLO
VIN VIN R
R
R
8310 F
8310f
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duty cycle should be checked for feasibility and margin over the full VIN operating range. The minimum input volt- age produces the maximum duty cycle, which must not exceed the LT8310’s minimum-specified maximum duty cycle limit (75%). The maximum input voltage produces the minimum duty cycle, which must be greater than duty cycle of the minimum GATE pulse width, f (^) SW • tON(MIN), as in Equation 14.
fSW • t (^) ON(MIN) <
VOUT(TARG)
VIN
NP
NS
< 0.75 [14]
Finally, the duty cycle scaling must be programmed. As discussed in the latter part of the section, Duty Mode Control, the voltage difference between the INTVCC and RDVIN pins, V (^) SET, and an accurate internal gain of 12V/V sets the duty mode loop scaling constant, KD. The RDVIN pin sinks a precise 20μA that permits a single resistor, RSET, to program the voltage difference.
KD =
12V
V
• VSET =
12V
V
Resistor RSET may be chosen to achieve the desired VOUT(TARG) based on Equation 16.
RSET =
VOUT(TARG)
12V / V
NP
NS
20μA
[16]
The tolerance of the set resistor contributes directly to the accuracy of the target output voltage, which is especially important to the accuracy of converters operating without output voltage feedback, so always use a 1% or better resistor. Keep RSET close to the RDVIN and INTVCC pins of the chip to minimize trace length and avoid cross-coupling with other signals.
During soft-start, the RDVIN sinking current is reduced to fold back the duty cycle while the clock frequency is also reduced. This protects the transformer by limiting the volt-seconds of flux generated when the clock period is made longer. Take care to consider the flux conditions during soft-start if external currents are employed for trimming or margining.
Programming the Switching Frequency The RT frequency adjust pin allows the user to program the switching frequency from 100kHz to 500kHz to optimize efficiency and performance or external component size. Higher frequency operation yields smaller component size, but increases switching losses and gate driving current, and may not allow sufficiently high or low duty cycle operation. It also decreases magnetization current, which reduces the minimum load requirement under duty cycle mode control. Lower frequency operation gives bet- ter performance at the cost of larger external component size. Table 1 shows the RT values for several frequencies that match the design equation, Equation 17. Table 1. Resistor Selection Guidance for Some Common Switching Frequencies FREQUENCY (fSW) (kHz)
PERIOD (tSW) (μs)
CLOSEST 1% RESISTOR (RT ) (kΩ) 100 10.0 100 150 6.67 66. 200 5.00 49. 250 4.00 40. 300 3.33 33. 350 2.86 28. 400 2.50 24. 450 2.22 22. 500 2.00 20.
R T =
1000kHz fSW
Minimize stray-coupling to the adjacent DFILT and SYNC pins by keeping the traces short. An external resistor from the RT pin to GND is required—do not leave this pin open.
Programming the Current Sense The LT8310 features primary-side switch current sensing that protects the system from excessive load current, damps output ringing when duty mode control dominates, and sets the duty cycle when current mode control dominates. When VSENSE exceeds 125mV (nom), the maximum switch current threshold, the system shuts down and attempts a restart after a slow wake-up period (see Programming the Soft-Start Interval and Hiccup Period). In converter
8310f
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applications operating without output voltage feedback, current sense information is fed back to the duty cycle loop to reduce output voltage ringing due to load current steps that excite the output LC tank. In supply applications, each cycle ends when the amplified SENSE voltage exceeds the V (^) C pin control level. In all cases, during the cycle on-time, the switch sees the rippling inductor current (I (^) L1), scaled by the transformer turns ratio (Equation 18) plus the transformer’s primary magnetizing current, Iμ,p. Applying VIN across the magnetizing inductance generates a peak magnetizing current of approximately 12 • VSET • tSW/Lμ,p.
ISWITCH =
IL
NP / NS
Resistor R (^) SENSE connected between the SENSE and GND pins converts the switch current to a voltage. It should be selected to provide the maximum switch current required by the application, including inductor ripple current, without exceeding the SENSE pin’s overcurrent threshold. A good rule of thumb is to allow 10% margin on the minimum overcurrent threshold of 115mV.
During steady-state operation, the average inductor current equals the load current. In applications under duty mode control, which require a minimum load, less inductor ripple means a lower minimum load current, so peak inductor current might be 10% or less above the maximum load current. Output voltage ring damping operates best with a strong average current signal, so R (^) SENSE should be chosen as large as allowed by the SENSE pin threshold. Equation 19 provides a good value for RSENSE that accounts for the minimum SENSE threshold:
RSENSE ≤ 115mV 1.1• I (^) SWITCH(MAX)
[19]
In applications with output voltage feedback, current mode control is most agile with a steep slope to the ripple, so peak inductor current might be 20% or more above the average load current. Equation 20 provides a good value for R (^) SENSE that accounts for the minimum SENSE threshold:
RSENSE ≤
115mV 1.4 • I (^) SWITCH(MAX)
[20]
It is always prudent to verify the peak inductor current in the application to ensure the sense resistor selection provides margin to the SENSE overcurrent limit threshold. The placement of RSENSE should be close to the source of the N-channel MOSFET and GND of the LT8310. The SENSE input to LT8310 should be a Kelvin connection to the positive terminal of R (^) SENSE. Verify the power in the resistor to ensure that it does not exceed its rated maximum.
Programming the Soft-Start Interval and Hiccup Period The built-in soft-start circuit significantly reduces the inrush current spike and output voltage overshoot at start-up. Please refer to Figure 6 and the Timing Diagrams section for the following discussion of soft-start behavior. The soft-start interval is programmed by a capacitor connected from the SS pin to GND. In a normal start-up, after the INTVCC voltage exceeds its rising threshold of about 5.2V, the SS pin sources 50μA (typical), which ramps the capacitor voltage. Switching commences when the 1.00V switching threshold is exceeded (EN_GATE high). Assuming the SS pin starts fully discharged, the soft-start time, t (^) SS, may be programmed by choosing CSS using Equation 21. A 100nF soft-start capacitor produces about 2ms of delay, which suits many applications.
CSS = 50nF •
tSS [ms ]
1ms
[21]
The SS pin voltage is discharged when the fault latch is set under any of the following conditions: the UVLO pin voltage falls below its threshold (SYS_UV high), the OVLO pin voltage exceeds its threshold (SYS_OV high), the die temperature exceeds 165°C (SYS_OT high), the INTVCC voltage falls below or rises above its operating range (REG_UV or REG_OV high), or the SENSE pin voltage exceeds its maximum threshold because the switch current is too large (ISW_MAX high). When the fault condition ceases and VSS < 0.27V, the fault latch clears, which brings about restart as SS rises through the 1V threshold. Exceeding maximum switch current sets the hiccup latch, which extends the soft-start time by reducing the pull-up current to 5μA (typical). After the fault latch is reset, the
