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CS433G: Computer System Organization, Spring 2007
Homework 1
Due at 9:30am, Thursday, Feb. 22
nd
On-line students:
Please send your solutions to [email protected] by due time. PDF is preferred. In your
email please indicate alias you would like to use.
On-campus students:
Please print this page and attach to your solutions. Write down your name, NetID and
alias. Hand in your solutions at the beginning of the class.
Everyone:
You must read and obey course policies. Policies can be found at:
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Problem Max Points 1a. 5 1b. 5 1c. 5 1d. 5 1e. 5 1f. 5 1g. 5 1h. 5 2a. 12 2b. 12 2c. 12 2d. 12 2.e 12 Total: 100
1. For this task you will need to perform binary operations, indicate if result has overflow or carry. You have the following binary numbers: A: 100001 B: 111111 a) Assume unsigned numbers. Show A+B.
^^
Overflow. Carry.
b) Assume unsigned numbers. Show A-B.
Overflow. Borrow (Carry).
c) Assume signed numbers. Show A+B.
No Overflow.
d) Assume signed numbers. Show A*B.
Answer: 011111
No Overflow.
e) Assume signed numbers and saturating arithmetic. Show (A+B)+A.
^^
Overflow. Need to saturate.
Answer: 0111.
2. Assume the architecture with the following instruction formats:
ADD R1, R2, R3 – register-register format ADD R1, R2, A – register-memory format (destination is a register) ADD A, R2, A - memory-register-memory (MRM) format (source and the same memory location)
Additionally architecture has generic load, store and branching instructions. There is a single memory addressing mode (base register + offset). Branches compare two registers and depending on comparison, move to target address. The target can be specified as PC relative offset or in a register. Assume the pipeline has this organization:
IF RF ALU1 READ ALU2 WRITE
Each pipeline stage takes one cycle. ALU1 is used for effective address calculation, for memory references and for branches. ALU2 used for branch comparison and arithmetic operations. Memory write and register write-back occur in the WRITE stage and memory read in the READ stage.
a) If there is only one port to memory (for both loads and stores), at what rate can we execute MRM format instructions? Justify your answer.
We can issue MRM instructions with the following pattern: MRM MRM Stall Stall ...
In every 4 instructions two can be MRM but then two must stall. The rate is 50% or in other words CPI=2.
b) Find the number of adders needed to minimize structural hazards. Count all adders and incrementors. Justify why this number is needed.
We need adders for ALU1 and ALU2. We would also benefit in case of branching if we can both calculate effective address and compare registers in ALU1. Therefore ALU1 should contain
additional adder for effective address calculation. Answer is 3.
c) How many read and write ports register file needs to minimize structural hazards? Justify your answer.
We need 3 read ports and 1 write port. Read ports are needed for a branch instruction that uses 3 registers. Write port is needed for WRITE stage.
d) How many read and write ports memory needs to minimize structural hazards? Justify your answer.
We need one port for READ stage and one port for WRITE stage. We do not have any other stages that access the memory and we do not have memory-memory instructions that need more ports.
e) Will data forwarding from ALU2 stage to ALU1, ALU2 or READ stage help to avoid stalls? Give example for each stage when such forwarding would be helpful.
We need data forwarding for all mentioned stages. ALU2->ALU1: ADD R1,R2,R ... ... ADD R4,R1,R
ALU2->ALU2: ADD R1,R2,R ADD R4,R1,R
ALU2->READ: ADD A,R1,A ... ADD R1,R2,A
