14 Practice Problems on Digital Circuits - Homework 6 | ENGR 160, Assignments of Microelectronic Circuits

Material Type: Assignment; Class: DIGITAL CIRCUITS; Subject: Engineering; University: Eastern Washington University; Term: Winter 2009;

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Pre 2010

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Winter 2009
ENGR 160 – DIGITAL CIRCUITS
Department of Engineering & Design at Eastern Washington University
HOMEWORK #6
DUE: February 24, 2009
NOTE: Long homework, but a lot of extra time to complete it.
THE NEXT 4 QUESTIONS ADDRESS THE FOLLOWING COURSE LEARNING OBJECTIVES:
Upon completion of this course, students will be able to:
Calculate gate level minimization algebraically and with advanced methods.
Describe the operation of each type of basic logic gate.
1. (10 pts) Express the following function with 2 and gates and an XOR gate:
F(A,B,C,D) = (3, 7, 11, 12, 13, 14)
2. (10 pts) Express the following function with no more than three two-input gates. You may not use inverters.
F(A,B,C,D) = AC’+A’D+ABC’+A’BCD+ABC’D
3. (10 pts) Express the following function using two XOR gates and one two-input AND gate:
F(A,B,C,D) = AB’CD’ + A’BCD’ + AB’C’D + A’BC’D
4. (10 pts) Express the following function using two XOR gates and one two-input AND gate:
F(A,B,C,D) = (5, 6, 8, 9, 10, 11, 12, 15)
THE NEXT QUESTIONS ADDRESS THE FOLLOWING COURSE LEARNING OBJECTIVES:
Upon completion of this course, students will be able to:
Describe and utilize each one of the combinational logic devices.
Design and optimize complex combinational logic circuits.
5. (10 pts) Derive the circuits for a three-bit parity generator and four-bit parity checker using odd parity bit (Read in
text what a parity bit is).
6. (10 pts) Implement all of the following four Boolean expressions with only three half adders, i.e. you may use
ONLY THREE half adders for this whole problem (not three for each function):
D(A,B,C) = A
B
C
E(A,B,C) = A’BC + AB’C
F(A,B,C) = ABC’ + (A’ + B’)C
G(A,B,C) = ABC
7. (10 pts) Design a combinational circuit with three inputs and one output. The output is 1 when the binary value of
the inputs is less than three. The output is 0 otherwise.
8. (10 pts) Design a combinational circuit with three inputs (x, y, and z), and three outputs (A, B, and C). When the
binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6, or 7,
the binary output is one less than the input.
9. (10 pts) A majority circuit is a combinational circuit whose output is equal to 1 if the input variables have more 1’s
than 0’s. The output is 0 otherwise. Design a 3-input majority circuit.
10. (10 pts) Design a 2 bit binary multiplier (i.e. a circuit that multiplies 2 two-bit binary numbers). Note: Clearly
indicate how many inputs and outputs the multiplier will have. Show both the function expression and the logic
diagram.
11. (10 pts) Design a 4-bit combinational circuit incrementer. This circuit adds one to a 4 bit binary number, i.e. the
decimal output is equal to the decimal input plus one. For example, if the input is 10012, the output should be 10102.
Note that the circuit can be implemented with 4 half adders.
12. (10 pts) Design a 4 bit combinational circuit 2’s complementer. The output should generate the 2’s complement of
the input binary number.
13. (10 pts) Implement a full subtractor using a 3-to-8 decoder.
14. (10 pts) Use two 4-to-1 multiplexers to implement a full adder.

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Winter 2009

ENGR 160 – DIGITAL CIRCUITS

Department of Engineering & Design at Eastern Washington University HOMEWORK # DUE: February 24, 2009 NOTE: Long homework, but a lot of extra time to complete it. THE NEXT 4 QUESTIONS ADDRESS THE FOLLOWING COURSE LEARNING OBJECTIVES: Upon completion of this course, students will be able to:  Calculate gate level minimization algebraically and with advanced methods.Describe the operation of each type of basic logic gate.

  1. (10 pts) Express the following function with 2 and gates and an XOR gate: F(A,B,C,D) = (3, 7, 11, 12, 13, 14)
  2. (10 pts) Express the following function with no more than three two-input gates. You may not use inverters. F(A,B,C,D) = AC’+A’D+ABC’+A’BCD+ABC’D
  3. (10 pts) Express the following function using two XOR gates and one two-input AND gate: F(A,B,C,D) = AB’CD’ + A’BCD’ + AB’C’D + A’BC’D
  4. (10 pts) Express the following function using two XOR gates and one two-input AND gate: F(A,B,C,D) = (5, 6, 8, 9, 10, 11, 12, 15) THE NEXT QUESTIONS ADDRESS THE FOLLOWING COURSE LEARNING OBJECTIVES: Upon completion of this course, students will be able to:  Describe and utilize each one of the combinational logic devices.Design and optimize complex combinational logic circuits.
  5. (10 pts) Derive the circuits for a three-bit parity generator and four-bit parity checker using odd parity bit (Read in text what a parity bit is).
  6. (10 pts) Implement all of the following four Boolean expressions with only three half adders, i.e. you may use ONLY THREE half adders for this whole problem (not three for each function):

D(A,B,C) = A  B  C

E(A,B,C) = A’BC + AB’C

F(A,B,C) = ABC’ + (A’ + B’)C

G(A,B,C) = ABC

  1. (10 pts) Design a combinational circuit with three inputs and one output. The output is 1 when the binary value of the inputs is less than three. The output is 0 otherwise.
  2. (10 pts) Design a combinational circuit with three inputs (x, y, and z), and three outputs (A, B, and C). When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6, or 7, the binary output is one less than the input.
  3. (10 pts) A majority circuit is a combinational circuit whose output is equal to 1 if the input variables have more 1’s than 0’s. The output is 0 otherwise. Design a 3-input majority circuit.
  4. (10 pts) Design a 2 bit binary multiplier (i.e. a circuit that multiplies 2 two-bit binary numbers). Note: Clearly indicate how many inputs and outputs the multiplier will have. Show both the function expression and the logic diagram.
  5. (10 pts) Design a 4-bit combinational circuit incrementer. This circuit adds one to a 4 bit binary number, i.e. the decimal output is equal to the decimal input plus one. For example, if the input is 1001 2 , the output should be 1010 2. Note that the circuit can be implemented with 4 half adders.
  6. (10 pts) Design a 4 bit combinational circuit 2’s complementer. The output should generate the 2’s complement of the input binary number.
  7. (10 pts) Implement a full subtractor using a 3-to-8 decoder.
  8. (10 pts) Use two 4-to-1 multiplexers to implement a full adder.