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Exam C
Question 1. Which component of the computer architecture is primarily responsible for executing instructions? A) Memory B) CPU C) I/O Device D) Cache Answer: B Explanation: The CPU (Central Processing Unit) is responsible for executing instructions, performing computations, and controlling data flow within the system. Question 2. In modern computer architecture, technology scaling primarily affects which of the following? A) Increasing physical size of components B) Enhancing power consumption C) Improving performance and reducing transistor size D) Reducing the number of transistors Answer: C
Exam C
Explanation: Technology scaling involves shrinking transistor sizes, which enhances performance, reduces power consumption, and allows for more transistors per chip. Question 3. Which performance metric measures the total time taken for a system to complete a task? A) Throughput B) Latency C) Response time D) Execution time Answer: D Explanation: Execution time measures the total time for a program or task to complete, reflecting system performance. Question 4. According to Amdahl's Law, the maximum speedup of a system is limited by which factor? A) The number of processors B) The sequential portion of the workload C) The clock speed
Exam C
B) To manage data storage in registers C) To generate control signals based on instruction decoding D) To fetch instructions from memory Answer: C Explanation: The control unit interprets instructions and generates appropriate control signals to coordinate datapath operations. Question 7. Which control method involves hardwired logic to generate control signals? A) Microprogrammed control B) Hardwired control C) Software control D) Sequential control Answer: B Explanation: Hardwired control uses fixed logic circuits to generate control signals, offering fast operation but less flexibility. Question 8. During instruction fetch, decoding, and execution stages, which stage typically involves accessing the register file?
Exam C
A) Fetch B) Decode C) Execute D) Write-back Answer: B Explanation: During decoding, the instruction is interpreted, and register file access occurs to read source operands. Question 9. Which addressing mode involves specifying the memory address directly within the instruction? A) Immediate B) Register C) Direct D) Indirect Answer: C Explanation: Direct addressing mode specifies the exact memory address within the instruction.
Exam C
Question 12. Forwarding or bypassing is a technique used to handle which type of hazard? A) Structural hazard B) Data hazard C) Control hazard D) Resource hazard Answer: B Explanation: Forwarding supplies the needed data directly from pipeline stages to avoid delays caused by data hazards. Question 13. Static branch prediction primarily relies on which of the following? A) Dynamic history B) Fixed prediction based on static analysis C) Machine learning algorithms D) Random choice Answer: B Explanation: Static prediction uses predetermined strategies, such as predicting backward branches as taken, without dynamic history.
Exam C
Question 14. Which branch prediction scheme uses a 2-bit counter to track branch behavior? A) Static prediction B) One-bit predictor C) Two-bit predictor D) Branch target buffer Answer: C Explanation: Two-bit predictors maintain a 2-bit counter, allowing for more accurate predictions by correlating past behavior. Question 15. In a superscalar processor, what is the key characteristic? A) Single instruction issue per cycle B) Multiple instructions issued per cycle C) Strict in-order execution D) RISC-only instruction set Answer: B Explanation: Superscalar processors issue multiple instructions simultaneously to exploit ILP and improve throughput.
Exam C
Question 18. Which principle states that data often accessed together should be stored close in memory? A) Spatial locality B) Temporal locality C) Locality of reference D) Sequential access Answer: C Explanation: Locality of reference encompasses both temporal and spatial locality, emphasizing that nearby or recent data is likely to be reused. Question 19. Which cache mapping policy assigns each block to exactly one cache line based on address bits? A) Fully associative B) Set-associative C) Direct-mapped D) Random Answer: C Explanation: Direct-mapped caches assign each memory block to a specific cache line determined by address bits, simplifying hardware.
Exam C
Question 20. Which cache replacement algorithm replaces the least recently used block? A) FIFO B) LFU C) LRU D) Random Answer: C Explanation: LRU (Least Recently Used) replaces the cache block that has not been accessed for the longest time, aiming to keep frequently accessed data. Question 21. Which virtual memory component translates virtual addresses to physical addresses? A) Page table B) TLB (Translation Lookaside Buffer) C) Cache D) Memory controller Answer: B Explanation: The TLB caches recent address translations, speeding up virtual- to-physical address conversion.
Exam C
Question 24. Which I/O technique involves the device transferring data directly to memory without CPU intervention? A) Programmed I/O B) Interrupt-driven I/O C) Direct Memory Access (DMA) D) Polling Answer: C Explanation: DMA allows devices to transfer data directly to/from memory, freeing CPU resources. Question 25. Which RAID level provides striping with parity for fault tolerance? A) RAID 0 B) RAID 1 C) RAID 5 D) RAID 10 Answer: C Explanation: RAID 5 uses striping with distributed parity, providing fault tolerance with better storage efficiency.
Exam C
Question 26. Which classification in Flynn's taxonomy describes a computer with a single instruction stream and a single data stream? A) SISD B) SIMD C) MISD D) MIMD Answer: A Explanation: SISD (Single Instruction, Single Data) refers to traditional sequential computers. Question 27. Which type of shared-memory architecture allows multiple processors to access a common memory space? A) Distributed memory B) SMP (Symmetric Multiprocessing) C) Cluster D) MIMD Answer: B Explanation: SMP architectures feature multiple processors sharing a single coherent memory space.
Exam C
Question 30. Which multithreading technique involves switching among threads at very fine granularity, often on a cycle-by-cycle basis? A) Coarse-grained multithreading B) Fine-grained multithreading C) Thread-level speculation D) Hardware multithreading Answer: B Explanation: Fine-grained multithreading switches among threads every cycle, helping to hide latency. Question 31. Which architecture employs multiple cores on a single chip to improve performance and energy efficiency? A) SMP B) CMP (Chip Multiprocessor) C) SIMD D) MIMD Answer: B Explanation: CMPs integrate multiple cores on a single chip, enabling parallel processing and energy savings.
Exam C
Question 32. What is a primary challenge in software development for multi- core architectures? A) Managing cache coherence B) Balancing load across cores C) Handling synchronization and data sharing D) All of the above Answer: D Explanation: Software developers must handle cache coherence, load balancing, and synchronization to fully leverage multi-core systems. Question 33. Which architecture is designed primarily to exploit data-level parallelism via vector processing? A) SIMD B) SISD C) MISD D) MIMD Answer: A Explanation: SIMD (Single Instruction, Multiple Data) architectures execute the same instruction on multiple data elements simultaneously.
Exam C
Question 36. Which interconnection network topology connects nodes in a ring-like structure, allowing each node to connect to two neighbors? A) Mesh B) Torus C) Ring D) Hypercube Answer: C Explanation: Ring topology connects each node to two neighbors, forming a circular network. Question 37. Which property of an interconnection network measures how quickly data can traverse the network? A) Latency B) Bandwidth C) Bisection bandwidth D) Throughput Answer: A Explanation: Latency measures the time delay for data to travel from source to destination.
Exam C
Question 38. On-chip networks (NoC) are primarily used to connect which system components? A) CPU cores B) Memory modules C) I/O devices D) Network routers Answer: A Explanation: NoCs (Networks-on-Chip) connect multiple cores, caches, and other components within a chip. Question 39. Which technique aims to reduce overall power consumption in modern architectures? A) Dynamic voltage and frequency scaling (DVFS) B) Increasing clock speed C) Removing cache D) Increasing transistor size Answer: A Explanation: DVFS adjusts voltage and frequency dynamically to balance power and performance, reducing power consumption.
