ENEE 302h: Digital Electronics — Homework 2
1
1. Logic to Circuit to Layout
Convert the following logical expressions to schematic diagrams for static CMOS logic. Then
convert each to a rough layout assuming an n-well process (e.g. p-type wafer: nFETs can be built
directly on the wafer); you need only show wells for pFETs. The following is an example:
A. out = ~( (a • b) | c )
B. out = ~( (a | b) • c )
C. out = ~( a • b • (c | d) )
D. out = (a + b); cout = (a + b = 10
2
) (carry-out only; no carry-in)
[do the full circuit diagram, but do not spend more than 20 minutes trying to do the layout for
this; it is not simple AOI logic … make enough of an attempt to understand the difficulty of
dealing with inverted values]
VDD
output
A B
A
B
out = ~( a • b )
GND
VDD
OUT
n-well
a
b
poly
metal
active
well
via
Homework 2
ENEE 302h: Digital Electronics, Fall 2004
Assigned: Mon, Sep 20 Due: Mon, Sep 27
