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Necessary to understand basic electrical properties of the MOS transistor to design useful circuits. Deal with non-ideal devices.
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Jacob Abraham
September 8, 2020
Necessary to understand basic electrical properties of the MOS transistor to design useful circuits Deal with non-ideal devices Ensure that the circuits are robust Create working layouts Predict delays and power consumption As circuit dimensions scale down, electrical effects become more important, even for digital circuits 1.65 GHz square wave from an HDMI Interface (Source: Dunnihoo, EE Times Asia, 8/25/2005)
Positive voltage on Gate produces electric field across substrate – attracts electrons to the Gate and repels holes With sufficient voltage, region under Gate changes from p- to n-Type – conducting path between the Source and Drain Inversion layer is field-induced junction, unlike a PN junction which is metallurgical Horizontal component of electric field associated with Vds > 0 is responsible for sweeping electrons from channel to drain
Threshold Voltage The gate voltage at which conduction takes place is the Threshold Voltage, Vt Current flow occurs when the drain to source voltage Vds > 0 , and consists almost entirely of majority-carriers (electrons), that flow through the channel A depletion region insulates the channel from the substrate
Vgs > Vt, Vds = 0
Saturated Mode (Vds > Vgs − Vt)
Nonsaturated Mode Vds < Vgs − Vt
Moderately doped n- type substrate (or well) in which two heavily doped p+ regions, the Source and Drain, are diffused
Application of a negative gate voltage (w.r.t. source) draws holes into the region below the gate; channel changes from n to p-type (source-drain conduction path) Conduction due to holes; negative Vd sweeps holes from source (through channel) to drain
Charge is carried by electrons Carrier velocity ν proportional to lateral E- field between source and drain ν = μE μ is called mobility E = Vds/L Time for carrier to cross channel: t = L/ν
nMOS Linear I-V Current can be obtained from charge in channel and the time t each carrier takes to cross Ids = Qchannel t = μCox
(Vgs − Vt − Vds/2) Vds = β (Vgs − Vt − Vds/2) Vds
nMOS Saturation I-V If Vgd < Vt, channel pinches off near drain when Vds > Vdsat = Vgs − Vt Now drain voltage no longer increases with current Ids = β (Vgs − Vt − Vdsat/2) Vdsat
=
β 2 (Vgs − Vt)^2
All dopings and voltages are inverted for pMOS (compared with nMOS) Mobility μp is determined by holes Typically 2x-3x lower than that of electrons μn Thus pMOS must be wider to provide the same current Simple assumption, μ μnp = 2
Capacitance in CMOS circuits Two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion Interconnection wires also have (distributed) capacitance
Gate Capacitance Approximate channel as connected to source Cgs = oxW L/tox = CoxW L = CpermicronW Typical Cpermicron ≈ 2fF/μm
Off Region Vgs ≤ Vt; when the MOS device is off, only Cgb (due to the series combination of gate oxide and depletion layer capacitance) is non-zero. Cgb = Cox = A/tox, where A is the gate area, and = 0 SiO 2 0 is the permittivity of free space ( 8. 854 × 104 F/m), and SiO 2 is the dielectric constant of SiO 2 (about 3.9)
Linear Region Depletion region exists, forming dielectric of depletion capacitance, Cdep in series with Cox As the device turns on, Cgb reduces to 0 The gate capacitance is now a function of the gate voltage
Saturated Region Region under the gate is heavily inverted, and drain region of channel pinched off, with Cgd reducing to zero Gate capacitance is now less than Cox
Approximation of Gate Capacitance For simplicity, we can assume the gate capacitance to be constant, Cg = A/tox
Have assumed that source is grounded
What happens if source > 0? Example, pass transistor passing VDD Vg = VDD If Vs > VDD − Vt, Vgs < Vt Hence, transistor would turn itself off
nMOS pass transistors pull no higher than VDD − Vt Called a degraded “1” Degraded value reached slowly in a transition (low Ids)
pMOS pass transistors pull no lower than Vtp Degraded “0”
What would be the voltages on the different nodes?
