Homework 3
Brief Solution
Problem 1
1. [1] The set of instructions that is examined for simultaneous execution is called the window.
[2] Window size decides the total number of instructions that can be examined for possible
independent instructions that can be issued together. Thus window size directly limits issue rate of the
processor, though it’s not the only factor. On the other hand, the window size is also limited by issue
rate from a practical point of view. A limited issue rate will make a large window size a waste and
much less helpful.
[2] Window size is limited by the required storage needed to put those instructions, and number of
comparisons needed to determine instruction dependences. Issue rate is limited by many other factors
like true data dependence among instructions in the window and limited number of functional units,
register file ports, instruction commit, etc.
2. [2] Fine-grained multithreading switches between threads on each instruction, causing the execution
of multiple threads to be interleaved at the granularity of one instruction. It takes the advantage that it
can fide the throughput losses that arise from both short and long stalls. The disadvantage of it is that
the execution of individual threads is slowed down.
[2] Coarse-grained multithreading switches threads only on costly stalls. It takes the advantage over
find-grained multithreading that it relieves the need to have thread switching be essentially free and is
much less likely to slow the processor down. The main drawback is that its ability to overcome
throughput losses, especially from shorter stalls, is limited.
3. [1] Since there is only one TLB, switching between processes lead to TLB flushing. Executing both
processes will make too many TLB flushes.
Problem 2
1. [5] 2 + (20% * 15% * 10 + 30% * 15% * 6) + (15% + 5%) * 5% * 50 = 3.07 (cycles)
15% load and of them 20% are close to store = 15%*20%*10
15% load and of them 30% are close to other = 15%*30%*6
stall penalty due to store->load = 0.15*0.20*10 = 0.3
stall penalty due to load->other = 0.15*0.30*6 = 0.27
stall due to cache miss = (0.15+0.05)*0.05*50 = 0.5
So, total penalty = 0.3+0.27+0.5 =1.07
CPI of A = 2+ 1.07 =3.07
2. [5] 2 + [80% * (20% * 15% * 1 + 30% * 15% * 1) + 20% * (20% * 15% * 10 + 30% * 15% * 6)] *
50% + (20% * 15% * 10 + 30% * 15% * 6) * 50% + 2% * 50% * 20% *50 + 3% * 20% * 50% * 50 =
2.622 (cycles)
20% data memory access = 15% load + 5% store ;20% of load have store->load delay 10
30% of load have load->other delay 6; 50% data memory are stack access(stack cache)
80% prediction in stack cache right then store-> load/load->other delay = 1
20% store->load=10 / load->other = 6; 2% = Miss rate for stack cache ; 3% = no-stack data access
miss rate.
