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Material Type: Assignment; Class: Digital Integ Circuits; Subject: Electrical & Computer Engr; University: Georgia Institute of Technology-Main Campus; Term: Spring 2004;
Typology: Assignments
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Homework No. 11 – Solutions
Problem 1 – P7.
OUT OL
X DD T
First, let’s find the required change in voltage:
OUT DD OL
X DD T DD T T
Now, let’s set up the clock feedthrough equation and solve for Cb:
b OUT X b X
X X T X b OUT X DD OL T
Problem 2 – P8.
To compute the device sizes, start
with the access transistor and the pull-down
transistor:
We can compute the needed size of
M 3 to deliver 300uA:
2 2 ( ) (^) (8)(1.6)(1.8 0.5 0.5) 300 ( ) (1.8 0.5 0.5) 1.
L sat ox DD OL TL L cell DD OL TL CN L
L
W m
Now determine the minimum WD for the pull-down transistor:
2 2
6 2
2 0.4 (min)
D N ox OL L sat ox DD OL TL DD T OL OL DD^ OL^ TL^ CN
CN
D cell
D D
W m L
−
M (^1)
M (^3)
Vdd
b
P8.4 - Continued
For the write operation, we must pull the internal node low against the PMOS pullup
device. Try forcing the output to 0.5V which is below the expected V (^) S.
2 6 2 (270)(1.6 10 ) 0. (3.75) 1.8 0.5 0.5 600 2 0.5 2 1 1
D N ox OL N DD T OL OL
CN
− × = (^) − − (^) = (^) − − (^) = (^) (^)
1.7 (max)
P sat ox DD TP L P DD TL CP
P
W m
Set Wp =0.75um.
Compute VS to ensure that the output will be below this value:
N
CN N N CP
P (^) P CN
CP P
S
Yes. This is still above the target V (^) OL so it should work just fine.
M (^4)
M (^6)
a
Gnd
b
Gnd