Homework 2
Please complete Problem 1, 2, 3, and 4 and turn these problems in at the beginning of
class on Monday, Sept 22.
The solutions to all questions will be posted after class on Monday so that you will have
the solutions to study for the exam. I suggest you try to work Problem 5 and 6 BEFORE
looking at the solutions.
For problems 2, 3, 5, and 6, please perform each of the following steps:
(a) Draw a symbol of the device showing all inputs and outputs.
(b) Develop a synthesizable verilog description.
(c) Develop a testbench to test the operation of the device
(d) Verify that your circuit meets specifications.
Please turn in all verilog code and a hardcopy of your simulation results. You can
demonstrate proper operation by either a printout of the “monitor” output (the table
printed once the simulation has been run) or by a printout of the waveforms (The results
of some problems are easier to see one way and the results of other problems are easier to
see another). Be sure to annotate your simulation results telling me how your results
prove that you have met all specifications.
Problem 1:
Provide a schematic of the circuit that the following Verilog description should produce.
Once you have produced the schematic, answer the following questions.
a) Could any lines of code be removed without changing the functionality?
Explain your answer
b) Under what conditions of A and B is the output 00002?
/*
* Module comb:
* performs combinational logic...
* what DOES it do?
*/
module comb( A, B, O );
// inputs
input [3:0] A, B;
// outputs
output [3:0] O;
// identifiers
wire cl, cg, ce;
reg [1:0] e;
reg [3:0] O;
/* Functionality */
assign cl = (A < B);
assign ce = (A == B);
