








Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
The final exam for the ece 398ssl course at the university of illinois urbana-champaign for the fall 2005 semester. The exam covers topics such as paging, segmentation, memory indirection, interrupt handling, task state, linux kernel, device abstraction, signals, interrupts, synchronization, and scheduling. The exam consists of 6 problems, some of which are multiple-choice, short answer, and coding questions.
Typology: Exams
1 / 14
This page cannot be seen from the preview
Don't miss anything!









For each question, circle the best answer. Each correct answer is worth 2 points, each incorrect answer is worth -½ points, so guess at your own risk. Questions left blank will be awarded 0 points. In all cases, assume an x86 processor running in protected mode is being used, and the version of Linux being used is 2.4.18 (like in the lab).
A. Driver abstraction B. Memory indirection C. Interrupt handling D. Task state
A. Hardware state (ie registers) for the new task must be loaded B. The value of the PBDR (cr3) must be changed C. Both A and B D. None of the above
A. Abstraction B. Sharing C. Performance D. Protection
A. Spinlock B. Reader/Writer spinlock C. Semaphore D. All of these can be safely acquired
A. (image+x1024+y) B. (image+xy) C. (image+y512+x) D. (image+x512+y)
function as the signal handler for SIGIO:
volatile int data; static semaphore_t sem; void signal_handler(int num) { int main(void) { ... ... down_semaphore(&sem); down_semaphore(&sem); //modify data //read data up_semaphore(&sem); up_semaphore(&sem); ... ... } }
What is the problem with this code? How could it be fixed?
This problem will focus on the x86 ENTER instruction. The instruction format and Intel pseudo-code are provided below:
ENTER imm imm16 is a 16-bit immediate value
Pseudo-code for the ENTER instruction (note that A refers to the first operand): IF StackSize = 32 THEN Push(EBP) ; Temp<- ESP; ELSE (* StackSize = 16) Push(BP); Temp <-SP; FI; IF StackSize = 32 THEN EBP <- Temp ESP <- EBP - A; ELSE ( StackSize = 16*) BP <- Temp SP <- BP - A; FI; END;
For this problem assume all code runs in protected (32-bit) mode.
(5 points) Part A: What is the high-level purpose of this instruction?
John is trying to cross Springfield Ave. Help him get across the street by completing the functions that
are prototyped for you below. When John, or any other person, tries to enter the crosswalk, they call
pedestrian_enter_crosswalk(). This function should not return until it is safe for the caller to enter the crosswalk. When this function returns, the pedestrian crosses the street and calls
pedestrian_leave_crosswalk() when they are safely on the other side. Similarly, the 26 Pack
(or any other vehicle) calls vehicle_enter_crosswalk() when it wants to cross. This function
should not return until it is safe for the vehicle to enter the crosswalk. When this function returns, the vehicle crosses and calls vehicle_leave_crosswalk() to signal that it is safely through the
crosswalk. For this problem, you can assume that the street is one lane and the crosswalk is narrow
enough that only one vehicle can be in it at a time. Also, cars (like pedestrians) do not have to cross in the order they arrive. You may use spin locks in your solution, but no other synchronization primitives.
struct crosswalk_t { //declare state variables here and indicate required initialization
void pedestrian_enter_crosswalk(struct crosswalk_t *c) {
void pedestrian_leave_crosswalk(struct crosswalk_t *c) {
void vehicle_enter_crosswalk(struct crosswalk_t *c) {
void vehicle_leave_crosswalk(struct crosswalk_t *c) {
Recall that if a page is marked as Global, a TLB entry corresponding to that page will not be flushed when cr3 is loaded, whereas non-global pages will have their TLB entry (if present) flushed whenever cr3 is loaded.
(5 points) Part A: Why do global pages exist? What is an example of where global pages would be useful?
(5 points) Part B: What is a scenario that would require a TLB entry for a Global page to be flushed?
Problem 5 (cont) (10 points) Part C: Remember that the Global flag only has an effect when the PGE (Page Global Enable) bit is set in cr4 (see picture below). Write the following function to flush ALL TLB entries. Assume that the PGE bit is set before your function is called.
//C prototype: void flush_all_tlbs(void); flush_all_tlbs:
void spin_lock_init (spinlock_t* lock); void spin_lock (spinlock_t* lock); void spin_unlock (spinlock_t* lock);
void sema_init (struct semaphore* sem, int val); void init_MUTEX (struct semaphore* sem); void init_MUTEX_LOCKED (struct semaphore* sem); void down (struct semaphore* sem); void up (struct semaphore* sem);
void rwlock_init (rwlock_t* rw); void read_lock (rwlock_t* rw); void write_lock (rwlock_t* rw); void read_unlock (rwlock_t* rw); void write_unlock (rwlock_t* rw);
void init_rwsem (struct rw_semaphore* sem); void down_read (struct rw_semaphore* sem); void down_write (struct rw_semaphore* sem); void up_read (struct rw_semaphore* sem); void up_write (struct rw_semaphore* sem);
void malloc(int size); / returns valid pointer on success, 0 on failure */ void free(void *mem);