CPSC 5155 Introduction to Computer Architecture
Mid-Term Exam Due Wednesday, October 22, 2008
1. (10 points) Prove or disprove the following claim, by any convenient means.
Show all work necessary to support your argument.
2. (15 points) Draw a circuit diagram to show how to implement
a) a three-input AND gate using only two-input AND gates.
b) a four-input AND gate using only three-input AND gates.
C) a three-input AND gate using only one four-input AND gate.
3. (25 points) Derive the state table and output table for the following circuit.
Use the assignments A = 00, B = 01, C = 10, and D = 11.
4. (10 points) Use a JK flip-flop and (possibly) a NOT gate to implement
a) a D flip-flop
b) a T flip-flop.
5. (20 points) Design a modulo–3 up counter (0, 1, 2, 0, 1, 2, etc).
Use D flip–flops. Allow for the unused state 3 to transition to state 0.
Do not draw the circuit, just show the equations for the D inputs to the flip–flops.
6. ( 10 points ) A certain computer has a 22–bit MAR. It uses word addressing, so
that the smallest addressable unit is 16 bits (two 8–bit bytes). What is the maximum
size of addressable memory, in bytes? Express either as a decimal number of power of 2.
Recall that 1MB = 220 bytes = 1, 048, 576 bytes.
7. (10 points) A cache memory has a SRAM cache with 4 nanosecond access time fronting for
a SDRAM main memory with access time of 60 nanoseconds.
If the effective access time is 9.6 nanoseconds, what is the hit rate?