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Part II
Addition / Subtraction
Number Representation
Numbers and ArithmeticRepresenting Signed Numbers Redundant Number SystemsResidue Number Systems
Addition / Subtraction
Basic Addition and CountingCarry-Look ahead Adders Variations in Fast AddersMultioperand Addition
Multiplication
Basic Multiplication SchemesHigh-Radix Multipliers Tree and Array MultipliersVariations in Multipliers
Division
Basic Division SchemesHigh-Radix Dividers Variations in DividersDivision by Convergence
Real Arithmetic
Floating-Point ReperesentationsFloating-Point Operations Errors and Error ControlPrecise and Certifiable Arithmetic
Function Evaluation
Square-Rooting MethodsThe CORDIC Algorithms Variations in Function EvaluationArithmetic by Table Lookup
Implementation Topics
High-Throughput ArithmeticLow-Power Arithmetic Fault-Tolerant ArithmeticPast, Present, and Future
Parts Chapters I.
II.
III.
IV.
V.
VI.
VII.
1.2. 3.4. 5.6. 7.8.
10.9. 11.12.
25.26. 27.28.
21.22. 23.24.
17.18. 19.20.
13.14. Elementary Operations 15.16.
- Reconfigurable Arithmetic Appendix: Past, Present, and Future
II Addition / Subtraction
Topics in This Part
Chapter 5 Basic Addition and Counting
Chapter 6 Carry-Lookahead Adders
Chapter 7 Variations in Fast Adder
Chapter 8 Multioperand Addition
Review addition schemes and various speedup methods
- Addition is a key op (in itself, and as a building block)
- Subtraction = negation + addition
- Carry propagation speedup: lookahead, skip, select, …
- Two-operand versus multioperand addition
5 Basic Addition and Counting
Chapter Goals
Study the design of ripple-carry adders,
discuss why their latency is unacceptable,
and set the foundation for faster adders
Chapter Highlights
Full adders are versatile building blocks
Longest carry chain on average: log 2 k bits
Fast asynchronous adders are simple
Counting is relatively easy to speed up
Key part of a fast adder is its carry network
Basic Addition and Counting: Topics
Topics in This Chapter
5.1 Bit-Serial and Ripple-Carry Adders
5.2 Conditions and Exceptions
5.3 Analysis of Carry Propagation
5.4 Carry Completion Detection
5.5 Addition of a Constant
5.6 Manchester Carry Chains and Adders
Half-Adder Implementations
Fig. 5.1 Three implementations of a half-adder.
c
s (b) NOR-gate half-adder.
x y
x y
(c) NAND-gate half-adder with complemented carry.
x
y
c
s
s
c x y x y
(a) AND/XOR half-adder. _
_
c _
Full-Adder Implementations
Fig. 5.2 Possible designs for a full-adder in terms of half-adders, logic gates, and CMOS transmission gates.
HA HA
y x
cin
cout
(a) Built of half-adders.
s
(b) Built as an AND-OR circuit.
(c) Suitable for CM OS realization.
cout
s
cin
y x
0 1 2 3
0 1 2 3
y x
cin
cout
s
0
1
M ux
Some Full-Adder Details
CMOS transmission gate and its use in a 2-to-1 mux.
z
x
x
0
1
(a) CMOS transmission gate: circuit and symbol
(b) Two-input mux built of two transmission gates
TG
TG TG
P^ y
N
Logic equations for a full-adder: s = x y c in (odd parity function) = x y c in x y c in x y c in x y c in
c out = x y x c in y c in (majority function)
Simple Adders Built of Full-Adders
Fig. 5.3 Using full-adders in building bit-serial and ripple-carry adders.
x y
c
x
s
y
c
x
s
y
c out c in
0 0
0
c 0
31
31
31
31
FA
s
c c
1 1
1
2 1 FA FA
s 32
x
s
y c c
i i
i
i +1 i CarryFF FA Shift
Shift
x
y
s
(a) Bit-serial adder.
(b) Ripple-carry adder.
Clock
Critical Path Through a Ripple-Carry Adder
Fig. 5.5 Critical path in a k -bit ripple-carry adder.
x
s
y
c
x
s
y
c
x
s
y
c
x
s
y
c
c out c in
0 0
0
c 0
1 1
1
1
k -2 k –^2
k – 2
k 2
k – 1
k – 1
k – 1
k – 1
FA FA.^.^. FA FA
ck – 2
sk
T ripple-add = T FA( x , y c out) + ( k – 2) T FA( c in c out) + T FA( c in s )
x y c c s
0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1
Inputs Outputs
c out c in
in out x y
s
FA
Binary Adders as Versatile Building Blocks
Fig. 5.6 Four-bit binary adder used to realize the logic function f = w + xyz and its complement.
c (^) 4 c (^) 3 c (^) 2 c (^) 1 c (^) 0
0 1 w 1 z 0 y x
Bit 3 Bit 2 Bit 1 Bit 0
w xyz
( w xyz )
w xyz xyz xy 0
Set one input to 0: c out = AND of other inputs
Set one input to 1: c out = OR of other inputs
Set one input to 0 and another to 1: s = NOT of third input
Saturating Adders
Saturating (saturation) arithmetic:
When a result’s magnitude is too large, do not wrap around; rather, provide the most positive or the most negative value that is representable in the number format
Designing saturating adders
Saturating arithmetic in desirable in many DSP applications
Saturation value
Overflow
0 1
Adder Unsigned (quite easy)
Signed (only slightly harder)
Example – In 8-bit 2’s-complement format, we have: 120 + 26 18 (wraparound); 120 +sat 26 127 (saturating)
5.3 Analysis of Carry Propagation
Bit positions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 0
c out 0 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 c in __________/__________________/ ________/____/ 4 6 3 2 Carry chains and their lengths Fig. 5.8 Example addition and its carry propagation chains.
5.4 Carry Completion Detection
Fig. 5.9 The carry network of an adder with two-rail carries and carry completion detection logic.
... ... ... ...
x y = x +y
alldone From other bit positions
i+
c = c
b = c
b = 1: No carry c = 1: Carry
b
c (^) i+1 0
i i i (^) i bi
c i
x + yi (^) i
x yi i
x yi i
0
in
in
}
di+1 i i
c (^) k = cout
bk
bi ci 0 0 Carry not yet known 0 1 Carry known to be 1 1 0 Carry known to be 0
5.5 Addition of a Constant: Counters
Count register
Mux
Incrementer (Dec rementer)
Data in
Load
Count / Initialize
_____
x + 1
x
0 1
Data out
Reset (^) Clear Clock Enable
Counter overflow
( x 1)
c out
Fig. 5.10 An up (down) counter built of a register, an incrementer (decrementer), and a multiplexer.
