Address Decoder, Binary Equivalent - Computer Architecture - Lecture Slides, Slides of Computer Architecture and Organization

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ADDRESS DECODER

address^ n lines

control^ r lines

fD

BLOCK DIAGRAM OF AN ADDRESS DECODER Docsity.com

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• Start by thinking of an address decoder as a big AND gate.
• We will call this a skeleton address decoder or SAD.
• Write the desired port address in binary.

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• Determine whether the decoder output should be active high or active low.
• Inver the output of SAD if active low is required.

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• Once the logic for the address decoder is established, the SAD can be implemented using any method of the logic design e.g., HDL or VHDL.

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• Start with a “big AND gate” (SAD).
• Write the address to be decoded (DEh) in binary.
• Thus, DEh → 1101 1110 b.

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1 1 0 1 1 1 1 0

A7 A6 A5 A4 A3 A2 A1 A

Address lines A15 .. A8 are don’t cares, and will not be used in this design.

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Control Line

fD

A

A

. . . A6 A

11

Control Line

fD

A

A

. .

IOW#

A A

13

fD

A

A

. .

IOW# (^) Control Line

A A

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• For a 16-bit output port, we use two 8-bit registers to capture data from the FALCON-A’s data bus.
• The output of the SAD will be connected to the enable inputs of the two registers.
• The D-inputs of the registers will be connected to the data bus.
• The Q outputs of the registers will be connected to the peripheral device.

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Continued…

Every LED branch is wired in such a way that when a 1 appears on the particular data bus bit, it turns the LED on; a 0 turns it off. Which LEDs will be ON when the instruction out r2, 222 executes on the CPU? Assume r contains 1234h.

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• r2 contains 1234h.
• The bit pattern corresponding to this value will be sent out to the output port at address 222.
• 222 is the address of the output port for this example.
• Writing the bit pattern in binary helps to determine the LEDs which will be ON.

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• The 8-bit register uses lines D15 .. D8 of the FALCON-A’s data bus.
• This register will be mapped onto the address DEh of theI/O space.
• The architect of the FALCON-A had chosen: 1): a “byte-wide” organization of the address space, 2): a 16-bit data bus width, 3): the “big-endian” data format at the ISA design stage.

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• D15...D8 will transfer the higher significance byte using the address DEh.
• D7...D0 will transfer the lower significance data byte using the address DFh.
• The LEDs at L12, L9, L5, L and L2 will turn on.