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Address translation, Virtual memory, Approach, Segmentation with paging, Paged page table, Memory hierarchy, Hash functions, Caching
Typology: Slides
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n Needs to be fast n Simplify memory allocation n Use fixed-sized objects instead of variable-sized objects n Avoid fragmentation (both internal and external) n Support sharing of code (or other pieces of program state) n Support incremental increase of stack, heap, etc. n Make translation table data structures inaccessible to user
n Simple, fast n But does not support sharing, incremental increase n Complex memory allocation
n Top few bits encode segment number. Each segment has a base and bounds. n Supports sharing and allows holes in virtual address space n Complex memory allocation
n Memory allocation done in small page sizes (4K – 16K) n Supports sharing n But need to allocate page table for entire virtual address space
VPage # offset
Virtual address
PPage # offset
Page table seg size
Vseg #
Each segment has its own page table
Supports sharing of segments, incremental growth of stack etc.
Almost simple memory allocation
n Need to lookup the segment table to do translation n To break “recursion,” make one of the segment table entries contain a physical pointer to a page table n In other words, all the page table of all segments live in a special segment VPage # offset
seg size
Vseg #
Virtual address
Physical address to segment’s page table
n Segment: 0x n Page number: 0x n Offset: 0xDEF
0x3 0x00000 0x 0x3 0x00100 0x 0x3 0x00200 0x 0x0 0x04010 0x
Segment table
VP1 off
Virtual address
seg size
VP2 off
Virtual address
VS
PPage # off
off2:
TranslateAddr(vaddr) { <seg1, page1, offset1> = vaddr; PTPtr = LookupSegmentTable(seg1); PTEPtr = PTPtr + page1 * sizeof(PTE); if (PTEPtr is virtual) PTEPtr = TranslateAddr(PTEPtr); PPageNumber = PTEPtr; // ignore permission bits paddr = PPageNumberpage_size + offset1; return paddr; }
n How do you find whether the item is in the cache or not? n If not in the cache, how do you choose what to replace from cache to make room? n Consistency – how do you keep cache copy consistent with real version?
Control Secondary Storage (Disk)
Processor
Registers Main Memory (DRAM)
Second Level Cache (SRAM)
CacheOn-Chip
1s 10,000,000s (10s ms)
Speed (ns): 10s 100s 100s Gs
Size (bytes): (^) Ks Ms
Tertiary Storage (Disk)
10,000,000,000s (10s sec) Ts
n Two principles: n Smaller the amount of memory, faster it can be accessed n Larger the amount of memory, cheaper per byte
n Temporal locality: will reference same locations as accessed in the recent past n Spatial locality: will reference locations near those accessed in the recent past
CPU
TLB remember? Yes No remember!
Translation Box
(MMU) physical memory
virtual address
physical address
Data read or write (untranslated)
n Restrict each virtual page to use specific slot in TLB
Vpage # Vpage #^ Ppage #
No: check full translation; replace entry
Yes Use translation
hash
n Table entry = (Vpage# / NUM_TLB_ENTRIES)
n Table entry = (Vpage# % NUM_TLB_ENTRIES)
n Requires more hardware n Translation can be store anywhere in TLB n Referred to as “fully associative”
Vpage # Vpage # Ppage #
hash
Vpage #Ppage #
n But for set associative or fully associative cache have a choice
n Least recently used? n Random? n Most recently used?
n Simple and fast
n Tradeoff: spend CPU cycles to try to improve cache hit rate
