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These are the Home Work of VLSI Physical Design Automation which includes First Gate, Edge Weighted, Undirected Graph, Number of Gates, Initial Partition, Best Cutsizes, Non Weighted Hypergraph, Single Pass, Area Constraint etc. Key important points are: Algorithm, First Gate, Edge Weighted, Undirected Graph, Number of Gates, Initial Partition, Best Cutsizes, Non Weighted Hypergraph, Single Pass, Area Constraint
Typology: Exercises
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NL 1 : n 1 = a–b–c, n 2 = b–d–e–f, n 3 = c–f–g, n 4 = a-g, n 5 = d-e–h, n 6 = f–h
a) Model the netlist with an edge-weighted undirected graph G 1. The edge weight is 1/(k-1) where k is the number of gates, e.g., 1/2 for n 1 and 1/3 for n (^2) b) Given an initial partition P 1 = { a,b,c,d | e,f,g,h } of G 1 , perform a single pass of KL algorithm. Give the cutsize after each swap. What are the initial, final, and best cutsizes?