Analog Cmos- Lecture13, Slides of Analog Electronics

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ECE 315/

Analog CMOS Circuit Design

Lecture 13

2 Outline

• Project teams & topics
• Basic Current Mirrors
• Cascode Current Mirrors

Conceptual means of copying currents

• Use of a reference to generate various currents.
• Two identical MOS devices that have equal gate-source voltages and operate in saturation carry equal currents

Basic Current Mirror Circuit

• Neglecting channel-length modulation, we can write
• Allows precise copying of the current with no dependence on process and temperature

Sizing Issues

• How do we generate a current equal to IREF /2=2 from IREF? Solutions: - a) half-width device b)series transistors

Current Mirrors as Signal Processors

• Current mirrors can process signals as well.
• Calculate the small-signal voltage gain of the circuit  Gain=

First Approach

• A cascode device can shield a current source
• Thereby reducing the voltage variations across it.
• But, how do we ensure that VDS2 = VDS1?
• We must generate Vb such that Vb - VGS3 = VDS1(= VGS1)

First Approach

• Place another diode-connected device M 0 in series with M 1

generates VN= VGS0 + VX

• Proper choice of dimensions of M 0 wrt M 3 , yields V GS

= V

GS

• Connecting node N to gate of M 3

, V

GS

+ V

X

= V

GS

+ V

Y

• If (W/L) 3

/(W/L)

0

= (W/L)

2

/(W/L)

1 , then V GS

= V

GS and V X

= V

Y

Approach summary

• In the figure on left side above
• Vb is chosen to allow the lowest possible value of VP
• But, output current does not accurately track IREF as V DS

≠ V

DS

• In the figure on right side above
• A higher accuracy is achieved
• But, minimum level at P is higher by one threshold voltage.

• In this case
• Following must be true for M0 and M1 to be saturated.
• A solution exists if
• Size M0 to ensure its overdrive is well below VTH
• If VGS0 = VGS3, and, Vb= VGS0 + VGS1 – VTH1 = VGS3 + VGS2 – VTH
• Circuit consumes minimum headroom and VDS2 ≈ VDS Low-voltage Cascode

Generate Vb

• Consider the branch shown in Fig(b) as a candidate and write V b

= VGS5 + R

6

I

6

• Ensure VGS5 = VGS3 by proper sizing
• However, following condition is hard to meet.

• Now consider branch in figure (c), if following can be ensured:
• Now possible to ensure that VGS6 and VGS1 track each other.
• For example, we may simply choose I 6 = IREF , R 6 = R 1 , and (W/L) 6 = (W/L) 1 Generate Vb

Generate Vb

• Diode-connected M7 has large W/L, so that VGS7 ≈ VTH VDS6 ≈ VGS6 - VTH Vb = VGS5 + VGS6 – VTH
• Circuit doesn't require any resistor but suffers from errors because of body effect

Example

• Voltage headroom is too small to allow the use of a cascode current source. Devise a method to reduce the current mirror error due to channel-length modulation.
• The voltages at P' and P track even if the CM level at A and B varies.
• The two differential pairs must incorporate the same lengths and scale their widths according to Wr/Wd = IREF/ISS.