EECS 140 Laboratory Exercise 6
Arithmetic Logic Unit
1. Objective
The objective of this laboratory is to apply knowledge of combinational logic designs to real
world application by implementing an arithmetic logic unit into a field programmable gate array chip.
2. Discussion
For this lab, you will use the Flex chip with predefined pin assignments on the Altera UP2
development board. The concept is to design and implement an arithmetic logic unit, which will
have the ability to take two four bit binary numbers and depending on a two bit selector either add,
logic AND, or logic OR the two inputs for a five bit binary output. You will use two seven-segment
displays to display the binary output in hexadecimal format. Your inputs will range from the
hexadecimal numbers 0 to F. Likewise, your outputs will range from 0 to 1E.
The easiest way to conceive the design for this circuit is to build it off your previous design
for an adder. Rather than designing the circuit at gate level, you may write behavioral VHDL.
You will re-use your 7-segment output block from Lab 5 for output, as well as the ripple-
carry adder. Make sure you design your ALU component with the inputs and outputs of your
existing components in mind.
3. Tasks
Step 1: Pre-Lab
You need to come to class with your design basics prepared. You should have a good idea of the
design concept as well as some basic Verilog. Think about how the logical AND and logical OR
units will fit in with your adder. Also consider which physical mechanism on the board could serve
as a way to select the operation that your ALU will perform.
Step 2
Draw a block diagram of your circuit. Include all of the arithmetic and logic elements, as well as
any multiplexers. Also include your seven-segment output components. Note that, in general,
input and output components are depicted separately from arithmetic or logic components.
