Arithmetic Logic Unit - Laboratory Exercise 6 | EECS 140, Lab Reports of Electrical and Electronics Engineering

Material Type: Lab; Professor: Ortiz; Class: Introd to Digital Logic Design; Subject: Elect Engr & Computer Science; University: University of Kansas; Term: Unknown 1989;

Typology: Lab Reports

Pre 2010

Uploaded on 09/17/2009

koofers-user-gpe
koofers-user-gpe 🇺🇸

10 documents

1 / 3

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
EECS 140 Laboratory Exercise 6
Arithmetic Logic Unit
1. Objective
The objective of this laboratory is to apply knowledge of combinational logic designs to real
world application by implementing an arithmetic logic unit into a field programmable gate array chip.
2. Discussion
For this lab, you will use the Flex chip with predefined pin assignments on the Altera UP2
development board. The concept is to design and implement an arithmetic logic unit, which will
have the ability to take two four bit binary numbers and depending on a two bit selector either add,
logic AND, or logic OR the two inputs for a five bit binary output. You will use two seven-segment
displays to display the binary output in hexadecimal format. Your inputs will range from the
hexadecimal numbers 0 to F. Likewise, your outputs will range from 0 to 1E.
The easiest way to conceive the design for this circuit is to build it off your previous design
for an adder. Rather than designing the circuit at gate level, you may write behavioral VHDL.
You will re-use your 7-segment output block from Lab 5 for output, as well as the ripple-
carry adder. Make sure you design your ALU component with the inputs and outputs of your
existing components in mind.
3. Tasks
Step 1: Pre-Lab
You need to come to class with your design basics prepared. You should have a good idea of the
design concept as well as some basic Verilog. Think about how the logical AND and logical OR
units will fit in with your adder. Also consider which physical mechanism on the board could serve
as a way to select the operation that your ALU will perform.
Step 2
Draw a block diagram of your circuit. Include all of the arithmetic and logic elements, as well as
any multiplexers. Also include your seven-segment output components. Note that, in general,
input and output components are depicted separately from arithmetic or logic components.
pf3

Partial preview of the text

Download Arithmetic Logic Unit - Laboratory Exercise 6 | EECS 140 and more Lab Reports Electrical and Electronics Engineering in PDF only on Docsity!

EECS 1 40 Laboratory Exercise 6

Arithmetic Logic Unit

1. Objective

The objective of this laboratory is to apply knowledge of combinational logic designs to real

world application by implementing an arithmetic logic unit into a field programmable gate array chip.

2. Discussion

For this lab, you will use the Flex chip with predefined pin assignments on the Altera UP

development board. The concept is to design and implement an arithmetic logic unit, which will

have the ability to take two four bit binary numbers and depending on a two bit selector either add,

logic AND, or logic OR the two inputs for a five bit binary output. You will use two seven-segment

displays to display the binary output in hexadecimal format. Your inputs will range from the

hexadecimal numbers 0 to F. Likewise, your outputs will range from 0 to 1E.

The easiest way to conceive the design for this circuit is to build it off your previous design

for an adder. Rather than designing the circuit at gate level, you may write behavioral VHDL.

You will re-use your 7-segment output block from Lab 5 for output, as well as the ripple-

carry adder. Make sure you design your ALU component with the inputs and outputs of your

existing components in mind.

3. Tasks

Step 1: Pre-Lab

You need to come to class with your design basics prepared. You should have a good idea of the

design concept as well as some basic Verilog. Think about how the logical AND and logical OR

units will fit in with your adder. Also consider which physical mechanism on the board could serve

as a way to select the operation that your ALU will perform.

Step 2

Draw a block diagram of your circuit. Include all of the arithmetic and logic elements, as well as

any multiplexers. Also include your seven-segment output components. Note that, in general,

input and output components are depicted separately from arithmetic or logic components.

Step 3

Write VHDL code for your circuit in Max+Plus II. You should only need to write the AND and OR

portions from scratch. You will also need to modify your top level design from Lab 2 in order to

accommodate the new components. Make sure you match cases when specifying names for input

and output pins in the module definition and the body of the module. Also make sure all of your

outputs are assigned a value at some point. Verify that the left hand side of any assignment is an

output.

You may use procedural statements (using process) to describe in VHDL the inputs and outputs

to each individual block. Remember that in practical application different pins are active-low and

active-high. Consult the pin out table in Figure 3.2. Pay very close attention to this detail.

Step 4

Once you have written your VHDL description of how the circuit should behave you should save

and simulate. Compile and simulate each component individually at first. Remember to select

“Generate Default Include File” from the File menu if you create or modify any files or

modules. Check the waveform against what the value of a given function should be. If you have

errors that need to be debugged, use the simulator to determine which outputs are not working

correctly. Look at the output waveform and compare it to the truth tables for 7-segment output.

Trace your design and fix any description errors. Consult your T.A. if needed.

Step 5

If your circuit simulates correctly then you can assign pins as you did in previous labs. Use the pin

assignment table in Figure 3.

Figure 3.1 Flex Chip Pin Assignments

Pin Name

Pin

Type Pin Function of Pin

MSD_dp OUTPUT 14 Most Significan Decimal Pt of Seven-Segment Display (0 = On) MSD_g OUTPUT 13 MSD G (0 = On) MSD_f OUTPUT 12 MSD F (0 = On) MSD_e OUTPUT 11 MSD E (0 = On) MSD_d OUTPUT 9 MSD D (0 = On) MSD_c OUTPUT 8 MSD C (0 = On) MSD_b OUTPUT 7 MSD B (0 = On) MSD_a OUTPUT 6 MSD A (0 = On) LSD_dp OUTPUT 25 Least Significant Decimal Pt of Seven-Segment Display (0 = On) LSD_g OUTPUT 24 LSD G (0 = On) LSD_f OUTPUT 23 LSD F (0 = On) LSD_e OUTPUT 21 LSD E (0 = On) LSD_d OUTPUT 20 LSD D (0 = On)